• 조명전기설비학회논문지
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• 제27권7호
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• pp.59-66
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• 2013

This paper proposes a new voltage reference generation method for Four-Switch Inverters(FSI) with compensation of the neutral DC-link voltage variation. Since FSIs have the split DC-link causing the inherent problem of voltage fluctuations in the upper and lower capacitors, it is required to take account the voltage difference between the top and bottom capacitors. In this paper, to reduce the effect by the voltage variation, reference voltages are modified by adding compensation voltages proportional to the voltage difference between upper and lower capacitors. Simulation results showing control performance of induction and permanent magnet motors demonstrate the validity of the proposed method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1044-1048
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• 2001

This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. This paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit id constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduce and the power factor improve. A circuit design method is shown by experimentation and confirmed simulation. It explained that compared conventional pulse-width modulated (PWM)inverter with half pulse-width modulated (HPWM) inverter proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.368-369
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• 2006

Ferroelectric thin films have attracted much attention for applications in nonvolatile ferroelectric random access memories(NVFeRAM) from the view points of high speed operation, low power consumption, and large scale Integration[1,2]. Among the FRAM, BLT is of particular interest. as it is not only crystallized at relatively low processing temperature, but also shows highly fatigue resistance and large remanent polarization Meanwhile, these submicron ferroelectric capacitors were fabricated by a damascene process using Chemical mechanical polishing (CMP). BLT capacitors were practicable by a damascene process using CMP. The P-E hysteresis were measured under an applied bias of ${\pm}5V$ by using an RT66A measurement system. The electric properties such as I-V were determined by using HP4155A analysers.

• ETRI Journal
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• 제28권4호
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• pp.486-494
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• 2006

Two current-mode and/or voltage-mode quadrature oscillator circuits each using one fully-differential second-generation current conveyor (FDCCII), two grounded capacitors, and two (or three) grounded resistors are presented. In the proposed circuits, the current-mode quadrature signals have the advantage of high-output impedance. The oscillation conditions and oscillation frequencies are orthogonally (or independently) controllable. The current-mode and voltage-mode quadrature signals can be simultaneously obtained from the second proposed circuit. The use of only grounded capacitors and resistors makes the proposed circuits ideal for integrated circuit implementation. Simulation results are also included.

• 대한전기학회논문지:전력기술부문A
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• 제55권6호
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• pp.242-248
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• 2006

This paper proposes a coordinated control method for under-load tap changers (ULTCs) with shunt capacitors to reduce the operation numbers of both devices. The proposed method consists of two stages. In the first stage, the dispatch schedule is determined using a genetic algorithm with forecasted loads to reduce the power loss and to improve the voltage profile during a day. In the second stage, each capacitor operates according to this dispatch schedule and the ULTCs are controlled in real time with the modified reference voltages considering the dispatch schedule of the capacitors. The performance of the method is evaluated for the modified IEEE 14-bus system. Simulation results show that the proposed method performs better than a conventional control method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 C
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• pp.1661-1663
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• 2001

This paper describes the dielectric characteristics of composite dielectric film for pulsed power capacitors. The relative electric permittivity(${\varepsilon}'$) and the dielectric dissipation factor(tan$\delta$) were measured for polypropylene (PP) membranes, kraft paper for capacitors(CP) and composite dielectric films(PP+CP), respectively, in a frequency range of $1{\sim}10^4$[Hz], and in temperatures ranging from -50[$^{\circ}C$] to 110[$^{\circ}C$]. As a result, the variation of the electric permittivity was observed similarly for PP and CP. Dielectric dispersion was observed in frequency domain in PP, CP and composite dielectric films.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 F
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• pp.2795-2797
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• 1999

Several power factor correction(PFC) circuits are presented to achieve high PF electronic ballast for both voltage-fed and current-fed electronic ballast. The proposed PFC circuits use valley-fill(VF) type DC-link stages modified from the conventional VF circuit to adopt the charge pumping method for PFC operations during the valley intervals. In voltage-fed ballast, charge pump capacitors are connected with the resonant capacitors. In current-fed type, the charge pump capacitors are connected with the additional secondary-side of the power transformer. The measured PF and THD are higher than 0.99 and 15% for all proposed PFC circuits. The lamp current CF is also acceptable in the proposed circuits. The proposed circuit is suitable for implementing cost-effective electronic ballast.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.963-966
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• 1999

This Paper describes the design of high speed and low power comparator based on the feed forward bias control. Major building blocks of this comparator are composed of input offset canceling circuit and feed forward bias control circuit. The usual offset canceling circuit cancels the offset voltages by storing them in capacitors using MOS switches, The comparator of this paper employs the bias control circuit which generates bias signal from the input signal. The bias signal is applied to the capacitors and keeps the transfer of chares in the capacitors in the minimal amount, therefore making the comparator operate in stable condition and reduce decision time. The comparator in this form has very samll area and power dissipation. Maximum sampling rate is 200 Ms/sec. The comparator is designed in 0.65${\mu}{\textrm}{m}$ technology and the offset is less than 0.5㎷.

• 한국결정성장학회지
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• 제12권3호
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• pp.161-164
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• 2002

Polycrystalline and epitaxial heterostructure films of $La_{0.5}Sr_{0.5}CoO_{3}/Pb(Nb_{0.04}Zr_{0.28}Ti_{0.68})O_{3}/La_{0.5}Sr_{0.5}CoO_{3}$ (LSCO/PNZT/LSCO) capacitors were evaluated in terms of low voltage and high speed operation in high density memory, using TiN/Pt conducting barrier combination. Structural studies for a high density ferroelectric memory process flow, which requires the integration of conducting barrier layers to connect the drain of the pass-gate transistor to the bottom electrode of the ferroelectric stack, indicate complete phase purity (i.e. fully perovskite) in both epitaxial and polycrystalline materials. The polycrystalline capacitors show lower remnant polarization and coercive voltages. However, the retention, and high-speed characteristics are similar, indicating minimal influence of crystalline quality on the ferroelectric properties.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.840-841
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• 2008

Power capacitors are widely used to compensate the low power factor of the linear load and/or nonlinear load. Especially, nonlinear loads generates the harmonic current and it gives an undesirable effect on the power capacitors. In this paper, harmonic current from nonlinear load to the power capacitors is calculated by the computer simulation and it is compared with the experimental results.