• IEIE Transactions on Smart Processing and Computing
• /
• v.4 no.3
• /
• pp.152-157
• /
• 2015

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.1
• /
• pp.71-80
• /
• 2015

LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.

• Journal of IKEEE
• /
• v.26 no.2
• /
• pp.313-318
• /
• 2022

The feedback voltage detection structure is proposed to alleviate overshoot and undershoot caused by the removal of the existing external output capacitor. Conventional LDO regulators suffer from overshoot and undershoot caused by imbalances in the power supply voltage. Therefore, the proposed LDO is designed to have a more improved transient response to form a new control path while maintaining only the feedback path of the conventional LDO regulator. A new control path detects overshoot and undershoot events in the output stage. Accordingly, the operation speed of the pass element is improved by charging and discharging the current of the gate node of the pass element. LDO regulators with feedback voltage sensing architecture operate over an input voltage range of 3.3V to 4.5V and have a load current of up to 200mA at an output voltage of 3V. According to the simulation result, when the load current is 200mA, it is 73mV under the undershoot condition and 61mV under the overshoot condition.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.16 no.9
• /
• pp.6247-6253
• /
• 2015

This paper presents the transient-response improved LDO regulator based on parallel error amplifiers. The proposed LDO regulator consists of an error amplifier (E/A1) which has a high gain and narrow bandwidth and a second amplifier (E/A2) which has low gain and wide bandwidth. These amplifiers are in parallel structure. Also, to improve the transient-response properties and slew-rate, some circuit block is added. Using pole-splitting technique, an external capacitor is reduced in a small on-chip size which is suitable for mobile devices. The proposed LDO has been designed and simulated using a Megna/Hynix $0.18{\mu}m$ CMOS parameters. Chip layout size is $500{\mu}m{\times}150{\mu}m$. Simulation results show 2.5 V output voltage and 100 mA load current in an input condition of 2.7 V ~ 3.3 V. Regulation Characteristic presents voltage variation of 26.1 mV and settling time of 510 ns from 100mA to 0 mA. Also, the proposed circuit has been shown voltage variation of 42.8 mV and settling time of 408 ns from 0 mA to 100 mA.