• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.209-215
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• 2001

In this paper a method for analysis and modelling of coplanar transmission interconnect lines that are placed on top of silicon-silicon oxide substrates is presented. The potential function is expressed by series expansions in terms of solutions of the Laplace equation for each homogeneous region of layered structure. The expansion coefficients of different series are related to each other and to potentials applied to the conductors via boundary conditions. In the plane of conductors, boundary conditions are satisfied at $N_d$ discrete points with $N_d$ being equal to the number of terms in the series expansions. The resulting system of inhomogeneous linear equations is solved by matrix inversion. No iterations are required. A discussion of the calculated line admittance parameters as functions of width of conductors, thickness of the layers, and frequency is given. The interconnect capacitance and conductance per unit length results are given and compared with those obtained using full wave solutions, and good agreement have been obtained in all the cases treated

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.8
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• pp.620-623
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• 2013

The carbon nanotube / poly-vinylidene fluoride (CNT/PVDF) composite films for the nano-generator devices were fabricated by spray coating method using the CNT/PVDF solution, which was prepared by adding PVDF pellets into the CNT dispersed N-Methyl-2-pyrroli-done (NMP) solution. The flexible CNT/PVDF composite films were investigated by the scanning electron microscopy, which revealed that the CNTs were uniformly dispersed in the PVDF matrix and thickness of the films was approximately $20{\mu}m$. Fourier transform infra-red spectra were used to investigate crystal structure of the as-spray-coated CNT/PVDF films, and we found that they revealed extremely large portion of the ${\beta}$ phase PVDF. The capacitance of the CNT/PVDF films increased by adding CNTs into the PVDF matrix, and finally saturated. However, the resistance didn't show any saturation effect in the CNT concentration range of 0~4 wt%. Finally, the resulting nano-generator devices revealed reasonable current output after given mechanical stress.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.12
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• pp.56-65
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• 2001

This paper proposes an algorithm for the capacitance extraction of general 3-dimensional conductors in an ideal uniform dielectric that uses a high-order quadrature approximation method combined with the typical first-order collocation method to enhance the accuracy and adopts an efficient matrix-vector product algorithm for the model-order reduction to achieve efficiency. The proposed method enhances the accuracy using the quadrature method for interconnects containing corners and vias that concentrate the charge density. It also achieves the efficiency by reducing the model order using the fact that large parts of system matrices are of numerically low rank. This technique combines an SVD-based algorithm for the compression of rank-deficient matrices and Gram-Schmidt algorithm of a Krylov-subspace iterative technique for the rapid multiplication of matrices. It is shown through the performance evaluation procedure that the combination of these two techniques leads to a more efficient algorithm than Gaussian elimination or other standard iterative schemes within a given error tolerance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.6
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• pp.131-139
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• 1989

This paper proposes Domino CMOS NOR-NOR Array Logic design method which has the same as characteristic of CMOS and Domino CMOS in Array Logic like PLA, good operation feature, high desity, easy test generation. This testable design method can detect all of faults in the circuit using simple additional circuit and solve the parasitic capacitance problem by improving the pull-down characteristics. A Test generation algorithm and test procedure using concept of PLA product term and personality matrix are proposed, and it was implemented in PASCAL language. This design method is verified by SPICE and P-SPICE simulation.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1582-1584
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• 1996

The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.45-55
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• 1999

The small signal analyzer for the stationary drift-diffusion equation is developed. The slotboom variables of the potential, electron and hole concentrations for the response of applied small signal are defined and the stationary drift-diffusion equation is linearlized on DC operation point by $S^3A$ method. Frontal solver, which is used to solve the global matrix, progresses the accuracy of the solution in high frequency and minimizes the requirement of the memory. The simulations are executed on the structure of 3 dimensional N'P junction diode and 2 dimensional n-MOSFET to verify the proposed algorithm. The average relative errors of the conductance and the capacitance compared with MEDICI are about 26% and 0.67 for N'P junction diode and 7.75% and 2.24% for n-MOSFET. The simulation by the proposed algorithm can analyze the stationary drift-diffusion equation for applied small signal in high frequency region about 100GHz.

• Korean Journal of Materials Research
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• v.24 no.5
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• pp.259-265
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• 2014

$ZrO_2$ films were coated on aluminum etching foil by the sol-gel method to apply $ZrO_2$ as a dielectric material in an aluminum(Al) electrolytic capacitor. $ZrO_2$ films annealed above $450^{\circ}C$ appeared to have a tetragonal structure. The withdrawal speed during dip-coating, and the annealing temperature, influenced crack-growth in the films. The $ZrO_2$ films annealed at $500^{\circ}C$ exhibited a dielectric constant of 33 at 1 kHz. Also, uniform $ZrO_2$ tunnels formed in Al etch-pits $1{\mu}m$ in diameter. However, $ZrO_2$ film of 100-200 nm thickness showed the withstanding voltage of 15 V, which was unsuitable for a high-voltage capacitor. In order to improve the withstanding voltage, $ZrO_2$-coated Al etching foils were anodized at 300 V. After being anodized, the $Al_2O_3$ film grew in the directions of both the Al-metal matrix and the $ZrO_2$ film, and the $ZrO_2$-coated Al foil showed a withstanding voltage of 300 V. However, the capacitance of the $ZrO_2$-coated Al foil exhibited only a small increase because the thickness of the $Al_2O_3$ film was 4-5 times thicker than that of $ZrO_2$ film.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.201-212
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• 2005

[ $Epoxy/BaTiO_3$ ] composite embedded capacitor films (ECFs) were newly designed fur high dielectric constant and low tolerance (less than ${\pm}15\%$) embedded capacitor fabrication for organic substrates. In terms of material formulation, ECFs are composed of specially formulated epoxy resin and latent curing agent, and in terms of coating process, a comma roll coating method is used for uniform film thickness in large area. Dielectric constant of $BaTiO_3\;&\;SrTiO_3$ composite ECF is measured with MIM capacitor at 100 kHz using LCR meter. Dielectric constant of $BaTiO_3$ ECF is bigger than that of $SrTiO_3$ ECF, and it is due to difference of permittivity of $BaTiO_3\;and\;SrTiO_3$ particles. Dielectric constant of $BaTiO_3\;&\;SrTiO_3$ ECF in high frequency range $(0.5\~10GHz)$ is measured using cavity resonance method. In order to estimate dielectric constant, the reflection coefficient is measured with a network analyzer. Dielectric constant is calculated by observing the frequencies of the resonant cavity modes. About both powders, calculated dielectric constants in this frequency range are about 3/4 of the dielectric constants at 1 MHz. This difference is due to the decrease of the dielectric constant of epoxy matrix. For $BaTiO_3$ ECF, there is the dielectric relaxation at $5\~9GHz$. It is due to changing of polarization mode of $BaTiO_3$ powder. In the case of $SrTiO_3$ ECF, there is no relaxation up to 10GHz. Alternative material for embedded capacitor fabrication is $epoxy/BaTiO_3$ composite embedded capacitor paste (ECP). It uses similar materials formulation like ECF and a screen printing method for film coating. The screen printing method has the advantage of forming capacitor partially in desired part. But the screen printing makes surface irregularity during mask peel-off, Surface flatness is significantly improved by adding some additives and by applying pressure during curing. As a result, dielectric layer with improved thickness uniformity is successfully demonstrated. Using $epoxy/BaTiO_3$ composite ECP, dielectric constant of 63 and specific capacitance of 5.1nF/cm2 were achieved.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.44-50
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• 2001

Metal oxide semiconductor (MOS) structures containing nanocrystals are fabricated by using rapid thermal oxidations of amorphous silicon films. The amorphous films are deposited either by electron beam deposition method or by electron beam deposition assisted by Ar ion beam during deposition. Post oxidation of e-beam deposited film results in relatively small hysteresis of capacitance-voltage (C-V) and the flat band voltage shift, $\DeltaV_{FB}$ is less than 1V indicative of the formation of low density nanocrystals in $SiO_2$ near $SiO_2$/Si interface. By contrast, we observe very large hysteresis in C-V characteristics for oxidized ion-beam assisted e-beam deposited sample. The flat band voltage shift is larger than 22V and the hysteresis becomes even broader as increasing injection times of holes at accumulation condition and electrons at inversion condition. The result indicates the formation of slow traps in $SiO_2$ near $SiO_2$/Si interface which might be related to large density nanocrystals. Roughly estimated trap density is $1{\times}10^{13}cm^{-2}$. Such a large hysteresis may be explained in terms of the activation of adatom migration by Ar ion during deposition. The activated migration may increase nucleation rate of Si nuclei in amorphous Si matrix. During post oxidation process, nuclei grow into nanocrystals. Therefore, ion beam assistance during deposition may be very feasible for MOS structure containing nanocrystals with large density which is a basic building block for single electron memory device.