• The KIPS Transactions:PartD
• /
• v.14D no.1 s.111
• /
• pp.139-144
• /
• 2007

In seeking to improve the workload efficiency and inference capability of context-aware systems, we propose a new framework for an advanced teaming mechanism that uses improved bath propagation (BP) algorithm. Even though a learning mechanism is one of the most important parts in a context-aware system, the existing algorithms focused on facilitating systems by elaborating the learning mechanism with user's context information are rare. BP is the most adaptable algorithm for learning mechanism of context-aware systems. By using the improved BP algorithm, the framework we proposed drastically improves the inference capability so that the overall performance is far better than other systems. Also, using the special system cache, the framework manages the workload efficiently. Experiments show that there is an obvious improvement in overall performanre of the context-awareness systems using the proposed framework.

• The KIPS Transactions:PartB
• /
• v.9B no.3
• /
• pp.303-310
• /
• 2002

In this paper, we propose a proxy caching scheme that stores a portion of a continuous media object or an entire object on the Internet. The proxy stores the initial fraction of a continuous media object and determines the optimal size of the initial fraction of the continuous media object to be cached based on the object popularity. Under the proposed scheme, the initial latency of most clients and the data transferred from a remote server can be reduced and limited cache storage space can be utilized efficiently. Considering the characteristics of continuous media, we also propose the novel popularity for the continuous media objects based on the amount of the data of each object played by the clients. Finally, we have performed trace-driven simulations to evaluate our caching scheme and the popularity for the continuous media objects. Through these simulations, we have verified that our caching scheme, PPC outperforms other well-known caching schemes in terms of BHR, DSR and replacement and that popularity for the continuous media objects based on the amount of the playback data can enhance the performance of caching scheme.

• The KIPS Transactions:PartA
• /
• v.12A no.3 s.93
• /
• pp.243-252
• /
• 2005

This paper introduces a noble modeling technique to build data communication prediction models in multiprocessors, using Least-Squares and Robust Estimation methods. A set of sample communication rates are collected by using a few small input data sets into workload programs. By applying estimation methods to these samples, we can build analytic models that precisely estimate communication rates for huge input data sets. The primary advantage is that, since the models depend only on data set size not on the specifications of target systems or workloads, they can be utilized to various systems and applications. In addition, the fact that the algorithmic behavioral characteristics of workloads are reflected into the models entitles them to model diverse other performance metrics. In this paper, we built models for cache miss rates which are the main causes of data communication in shared memory multiprocessor systems. The results present excellent prediction error rates; below $1\%$ for five cases out of 12, and about $3\%$ for the rest cases.

• Journal of KIISE:Computer Systems and Theory
• /
• v.27 no.1
• /
• pp.101-108
• /
• 2000

The data prefetching scheme is an effective technique to reduce the main memory access latency by exploiting the overlap of processor computations with data accesses. However, if the prefetched data replicate the useful existing data in the cache memory and they are not being used in computations. performances of programs are aggravated. This phenomenon results from the lack of correct predictions for data being used in the future. When parallel programs exploit the data arrays for computations, the grain size is useful information for data prefetching scheme because it implies the range of data using in computations. Based on this information, we suggest a new data prefetching scheme exploited by the grain size of the parallel program. Simulation results show that the suggested prefetching scheme improves the performance of the simulated parallel programs due to the reduction of bus transactions as well as useful prefetching operations.

• Journal of KIISE:Computing Practices and Letters
• /
• v.15 no.12
• /
• pp.968-972
• /
• 2009

The multi-core processors are being widely exploited by many high-end systems. With significant advances in processor architecture, the network band-width required on the high-end systems is increasing drastically. It is therefore highly desirable to manage multiple cores efficiently to achieve high network band-width with minimum resource requirements. Modern operating systems, however, still have significant design and optimization space to leverage the network performance over multi-core systems. In this paper, we suggest a novel networking process scheduling scheme, which decides the best processor affinity of networking processes based on the processor cache layout, communication intensiveness, and processor loads. The experimental results show that the scheduling scheme implemented in the Linux kernel can improve the network bandwidth and the effectiveness of processor utilization by 20% and 59%, respectively.

• KIISE Transactions on Computing Practices
• /
• v.21 no.1
• /
• pp.88-93
• /
• 2015

In modern computer systems, DRAM is commonly used as main memory due to its low read/write latency and high endurance. However, DRAM is volatile memory that requires periodic power supply (i.e., memory refresh) to sustain the data stored in it. On the other hand, PCM is a promising candidate for replacement of DRAM because it is non-volatile memory, which could sustain the stored data without memory refresh. PCM is also available for byte-addressable access and in-place update. However, PCM is unsuitable for using main memory of a computer system because it has two limitations: high read/write latency and low endurance. To take the advantage of both DRAM and PCM, a hybrid main memory, which consists of DRAM and PCM, has been suggested and actively studied. In this paper, we propose a novel page replacement algorithm for hybrid main memory. To cope with the weaknesses of PCM, our scheme focuses on reducing the number of PCM writes in the hybrid main memory. Experimental results shows that our proposed page replacement algorithm reduces the number of PCM writes by up to 80.5% compared with the other page replacement algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.11B
• /
• pp.911-919
• /
• 2004

IP address lookup is one of the essential functions on internet routers, and it determines overall router performance. The most important evaluation factor for software-based IP address lookup is the number of the worst case memory accesses. Binary prefix tree (BPT) scheme gives small number of worst case memory accesses among previous software-based schemes. However the tree structure of BPT is normally unbalanced. In this paper, we propose weighted binary prefix tree (WBP) scheme which generates nearly balanced tree, through combining the concept of weight to the BPT generation process. The proposed WBPT gives very small number of worst case memory accesses compared to the previous software-based schemes. Moreover the WBPT requires comparably small size of memory which can be fit within L2 cache for about 30,000 prefixes, and it is rather simple for prefix addition and deletion. Hence the proposed WBPT can be used for software-based If address lookup in practical routers.

• The Journal of Korean Association of Computer Education
• /
• v.13 no.1
• /
• pp.53-64
• /
• 2010

In this paper, we tried to enable a mobile device as a resource to access to mobile grid networks. By advanced Internet techniques, the use of mobile devices has been rapidly increased. Some researches in mobile grid computing tried to combine grid computing with mobile devices. However, according to intrinsic properties of mobile environments, mobile devices have many considerations, such as mobility management, disconnected operation, device heterogeneity, service discovery, resource sharing, security, and so on. To solve these problems, there are two trends for mobile grid computing: a proxy-based mobile grid architecture and an agent-based mobile grid architecture. We focus on a proxy-based mobile grid architecture with IP-paging, which can easily manage idle mobile devices and grid resource status information. Also, we use SIP(Session Initiation Protocol)to support mobility management, mobile grid services. We manage variation of mobile device state and power by paging cache. Finally, using the candidate set and the reservation set of resources, we perform task migration. The performance evaluation by simulation, shows improvement of efficiency and stability during execution.

• Journal of Digital Convergence
• /
• v.12 no.2
• /
• pp.277-283
• /
• 2014

Recently, various cloud service has been being provided on mobile devices as well as desktop pc and server computer. Also, Smartphone users are very rapidly increasing, and they are using it for enjoying various services(cloud service, game, banking service, mobile office, etc.). So, research to utilize resources on mobile device has been conducted. In this paper, We have suggested efficient method of cloud resource management by using information of available physical resources(CPU, memory, storage, etc.) between mobile devices, and information of physical resource in mobile device. Suggested technology is possible to guarantee real-time process and efficiently manage resources.

• The Journal of the Acoustical Society of Korea
• /
• v.19 no.4
• /
• pp.37-44
• /
• 2000

In this paper, we described the real-time implementation effort of MPEG-4 audio HVXC (Harmonic Vector eXcitation Coding) algorithm for very low bitrates, which has target applications from mobile communications to Internet telephony, on current high performance floating point TMS320C6701 DSP. We adopted a hardware structure for real-time operation. In order for software optimization, we used C- and assembly-language level optimizations for time-critical functional codes. Utilizing the internal program memory of the DSP as the program cache, the internal data memory overlap technique and DMA functionality, we could get a goal of realtime operation of HVXC codec both at 2 kbit/s and at 4 kbit/s. For an encoder at 2 kbit/s, the optimization ratio to original code is about 96 %. Finally, we got the subjective quality of MOS 2.45 at 2 kbit/s from an informal quality test.