• Journal of KIISE:Computer Systems and Theory
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• v.31 no.12
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• pp.704-715
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• 2004

Recently, a single or multi processor system uses the hierarchical memory structure to reduce the time gap between processor clock rate and memory access time. A cache memory system includes especially two or three levels of caches to reduce this time gap. Moreover, one of the most important things In the hierarchical memory system is the hit rate in level 1 cache, because level 1 cache interfaces directly with the processor. Therefore, the high hit rate in level 1 cache is critical for system performance. A victim cache, another high level cache, is also important to assist level 1 cache by reducing the conflict miss in high level cache. In this paper, we propose the advanced high level cache management scheme based on the processor reuse information. This technique is a kind of cache replacement policy which uses the frequency of processor's memory accesses and makes the higher frequency address of the cache location reside longer in cache than the lower one. With this scheme, we simulate our policy using Augmint, the event-driven simulator, and analyze the simulation results. The simulation results show that the modified processor reuse information scheme(LIVMR) outperforms the level 1 with the simple victim cache(LIV), 6.7% in maximum and 0.5% in average, and performance benefits become larger as the number of processors increases.

• The Journal of the Korea Contents Association
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• v.18 no.3
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• pp.70-80
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• 2018

Due to the recent development of social media and mobile devices, graph data have been using in various fields. In addition, caching techniques for reducing I/O costs in the process of large capacity graph data have been studied. In this paper, we propose a multi-layer caching scheme considering the connectivity of the graph, which is the characteristics of the graph topology, and the history of the past subgraph usage. The proposed scheme divides a cache into Used Data Cache and Prefetched Cache. The Used Data Cache maintains data by weights according to the frequently used sub-graph patterns. The Prefetched Cache maintains the neighbor data of the recently used data that are not used. In order to extract the graph patterns, their past history information is used. Since the frequently used sub-graphs have high probabilities to be reused, they are cached. It uses a strategy to replace new data with less likely data to be used if the memory is full. Through the performance evaluation, we prove that the proposed caching scheme is superior to the existing cache management scheme.

• Convergence Security Journal
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• v.12 no.4
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• pp.91-96
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• 2012

MANET is developed technique fairly among many field of wireless network. Nodes which consist of MANET transmit data using multi-hop wireless connection. Caching scheme is technique which can improve data access capacity and availability of nodes. Previous studies were achieved about dynamic routing protocol to improve multi-hop connection of moving nodes. But management and maintenance of effective cache information because of movement of nodes is not easy. In this study, we proposed cluster-based caching scheme to manage connection by decreasing overhead and moving of nodes as moving node discovers cache of wish information. And HLP was used to maintain effective cache table in each cluster head. Efficiency of proposed technique in this study was confirmed by experiment.

• Journal of Industrial Convergence
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• v.17 no.4
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• pp.131-137
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• 2019

In infrastructure wireless mesh networks (WMNs), in order to improve mobile users' satisfaction for the given cache hit ratio, we investigate an User centric Cache Allocation (UCA) scheme while reducing cache cost in a mesh router (MR) and expected transmission time (ETT) for content search in cache. To minimize ETT values of mobile users, a genetic algorithm based UCA (GA-UCA) scheme is provided. The goal is to maximize mobile users' satisfaction via our well defined utility, which considers content popularity and the number of mobile users. Finally, through solving optimization problem we show the optimal cache can be allocated for UCA and GA-UCA. Besides, a WMN provider can find the optimal number of mobile users for user centric cache allocation in infrastructure WMNs.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.285-291
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• 2010

Flash memory has many good features such as small size, shock-resistance, and low power consumption, but the cost of flash memory is still high to substitute for hard disk entirely. Recently, some mobile devices, such as laptops, attempt to use both flash memory and hard disk together for taking advantages of merits of them. However, existing OSs (Operating Systems) are not optimized to use the heterogeneous storage media. This paper presents a new buffer cache management scheme. First, we allocate buffer cache space according to access patterns of block references and the characteristics of storage media. Second, we prefetch data blocks selectively according to the location of them and access patterns of them. Third, we moves destaged data from buffer cache to hard disk or flash memory considering the access patterns of block references. Trace-driven simulation shows that the proposed schemes enhance the buffer cache hit ratio by up to 29.9% and reduce the total I/O elapsed time by up to 49.5%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.7
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• pp.1639-1649
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• 1998

For mobile multimedia services, wireless ATM(Asynchronous transfer Mode) network is studied actively. In wireless ATM network, the existing signaling protocols generate heavy traffics for HLR due to the centralized structure that all signaling loads mush be handled in HLR(Home Location Register). Also, centralized structure causes critical connection setup delays. Thus, it is important that wireless ATM reduces the connection setup delays occurred due to high traffic loads of signaling based on distributed processing. In this thesis, we propose a cache strategy for call delivery as well as the cache updates of registration based on ATM multicasting and compares the cost of cache scheme with that of conventional scheme. Our study shows that cache scheme has better performance than the conventional methods in the case that the portable mobility is low and traffic density is large.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.235-238
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• 2002

This paper proposes a novel scheme of designating non-cacheable addresses of memories in embedded systems of multi-master architectures without a Memory Management Unit (MMU). As a solution for data coherency problem between external memories and a cache memory, we proposes a cache masking scheme by allocating the most significant bit of address not used in 32-bit address system as indicator bit to designate non-cacheable address. As this scheme enables non-cacheable area designation every address, the simpler in the aspect of hardware and more flexible size of non-cacheable area can be obtained.

• Journal of the Korea Society of Computer and Information
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• v.17 no.5
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• pp.41-48
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• 2012

A Vehicular Ad-hoc Network (VANET) is a vehicular specific type of a mobile ad-hoc network, to provide temporary communications among nearby vehicles. Mobile node of VANET consumes energy and resource with participating in the member of network. In a VANET, data replication and cooperative caching have been used as promising solutions to improve system performance. Existing cooperative caching scheme in a VANET mostly focuses on weak consistency is not always satisfactory. In this paper, we propose an efficient cache management scheme to maintain strong data consistency in a VANET. We make an adaptive scheduling scheme to broadcast Invalidation Report (IR) in order to reduce query delay and communication overhead to maintain strong data consistency. The simulation result shows that our proposed method has a strength in terms of query delay and communication overhead.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.10 no.1
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• pp.95-105
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• 2006

The speed of hard disk which is based on mechanical operation is more slow than processor. The growth of processor speed is rapid by semiconductor technology, but the growth of disk speed which is based on mechanical operation is not enough. Buffer cache in main memory and disk cache in disk controller have been used in computer system to solve the speed gap between processor and I/O subsystem. In this paper, an efficient buffer cache and disk cache management scheme was proposed to restrict duplicated disk block between buffer cache and disk cache. The performance of the proposed algorithm was evaluated by simulation.

• Journal of KIISE:Databases
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• v.29 no.2
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• pp.148-157
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• 2002

Caching in meta-search engines can improve the response time of users' request. We describe the cache scheme in our meta-search engine in terms of its architecture and operational flow. In particular, we propose a popularity-driven cache algorithm that utilizes popularities of queries to determine cached data to be purged. The popularity is a value that represents the normalized occurrence frequency of user queries. This paper presents how to collect popular queries and how to calculate query popularities. An empirical performance evaluation of the popularity-driven caching with the traditional schemes (i.e., least recently used (LRU) and least frequently used (LFU)) has been carried out on a collection of real data. In almost all cases, the proposed replacement policy outperforms LRU and LFU.