• Proceedings of the Korean Information Science Society Conference
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• 2011.06a
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• pp.547-550
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• 2011

플래시 메모리는 낮은 전력 소비와 높은 성능으로 인해 휴대용 기기에 널리 사용되고 있다. FTL은 플래시 내 자료를 관리하는 소프트웨어 계층으로 플래시 전체의 성능에 영향을 끼친다. 그 중 페이지 레벨 매핑 기법을 적용한 FTL은 유연성이 높고 속도가 빠르나 주소 변환 테이블의 크기가 큰 단점이 있다. 이를 해결하기 위해 자주 접근되는 영역의 매핑 주소만을 매핑 테이블 캐시에 올려놓는 Demand-based FTL(DFTL)이 제안되었다. DFTL 에서는 CMT(Cache Mapping Table)의 참조율이 떨어지는 경우 빈번한 플래시 메모리 접근 오버헤드가 발생하게 된다. 이러한 문제는 흔히 발생하는 일반적인 순차 접근에서조차 문제가 된다. 이에 본 논문에서는 저장 장치의 접근 패턴을 예측하여 CMT의 참조 엔트리를 미리 읽어오는 기법을 제안한다. 제안하는 기법은 저장 장치 접근 패턴의 순차성을 판단하여 연속된 매핑 주소를 미리 CMT에 올려놓고, 읽어오는 매핑 주소 엔트리의 양은 동적으로 관리한다. 추가적으로 CMT에서 발생하는 스래싱(thrashing) 을 파악하기 위해 쫓겨나는 희생 엔트리의 접근 여부를 분석하여 이를 활용하였다. 실험 결과에서 본 기법은 기존의 DFTL에 비해 약간의 공간 오버헤드와 함께 평균 50% 증가한 참조율을 보였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.849-858
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• 2012

We proposed a scheme to accurately detect elephant flows. Along the ever increasing traffic trend, certain flows occupy the network heavily in terms of time and network bandwidth. These flows are called elephant flows. Elephant flows raises complicated issues to manage for Internet traffics and services. One of the methods to identify elephant flows is the Landmark LRU cache scheme, which improved the previous method of Least Recently Used scheme. We proposed a cache update algorithm, to further improve the existing Landmark LRU. The proposed scheme improves the accuracy to detect elephant flow while maintaining efficiency of Landmark LRU. We verified our algorithm by simulating on Sangmyung University's wireless real network traces and evaluated the improvement.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.7
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• pp.519-525
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• 2013

The traffic classification is a preliminary and essential step for stable network service provision and efficient network resource management. However, the payload signature-based method has a significant drawback in high-speed network environment that the processing speed is much slower than other method such as header-based and statistical methods. In this paper, We propose the server IP, Port cache-based traffic classification method using application traffic locality to improve the processing speed of traffic classification. The suggested method achieved about 10 folds improvement in processing speed and 10% improvement in completeness over the payload-based classification system.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1143-1152
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• 1999

A Mobile computing environment is a new paradigm which provides users with the access to information irrespective of users' location. A transaction scheduling method for the mobile computing environment must be designed so that database consistency is maintained with considering the limited performance of mobile hosts and the narrow bandwidth of a wireless network. The scheduling method using a lock has some problems: the high message overhead between a server and a mobile host for maintaining a lock and the high abort ratio of the mobile transactions owing to violating the serializability when a mobile host uses a cache. So, in this paper, we propose an efficient transaction management method using timestamp to resolve these problems. The proposed method is used in the environment under which a mobile host uses a cache having two versions for each cached data item and a server maintains several versions for each data item. So, even though a mobile transaction is executed during several broadcasting interval, can be committed. As a result, the proposed method can improve the commit ratio of the mobile transactions by maintaining multiversion for each data item and does not require the additional message exchange to schedule transactions by using timestamp.

• KIPS Transactions on Computer and Communication Systems
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• v.4 no.2
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• pp.41-46
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• 2015

The demand on low power and high performance system is soaring due to the extending of mobile and small electronic device market. The 3D die-stacking technology is widely studying for next generation integration technology due to its high density and low access time. We proposed the 3D die-stacked DRAM including a reconfigurable accelerator in a logic layer of DRAM. Also we discuss and suggest a cache-based local memory for a reconfigurable accelerator in a logic layer. The reconfigurable accelerator in logic layer of 3D die-stacked DRAM reduces the overhead of data management and transfer due to the characteristics of its location, so that can increase the performance highly. The proposed system archives 24.8 speedup in maximum.

• The KIPS Transactions:PartC
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• v.9C no.5
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• pp.789-798
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• 2002

Even when users are moving, a major problem in such a mobile networks is how to locate mobile clients. Two major operations are involved in managing a mobile client's location : the location registration operation and the call tracking operation. The past methods can only minimize the cost of one of these two operations, but not both. The contribution of this paper is to propose strategy that minimize the costs of both operations simultaneously. Our performance analysis proves that the proposed strategies are superior to the past methods.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11b
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• pp.1039-1042
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• 2003

웹 정보의 급격한 양적 팽창은 네트워크 병목 현상과 사용자의 지연시간 증가 및 웹 서버의 과부하 등의 문제를 야기하고 있다. 이를 완화시키기 위한 방법으로 웹 캐슁이 이용되는데, 전통적인 캐슁과는 달리 문서의 종류와 크기가 가변적이며 많은 사용자의 요구를 처리해야하는 특성이 있다. 따라서 본 논문에서는 동적인 웹 환경과 한정된 크기의 웹 캐쉬 공간의 사용 효율을 향상시켜 캐쉬 적중률을 증가시키기 위한 방법으로, 서비스되는 각 파일의 메타정보를 Main Server의 캐쉬에 리스트 형태로 유지하는 CRBM(Client Request Buffer Manager)을 제안한다.

• Proceedings of the Korea Contents Association Conference
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• 2019.05a
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• pp.461-462
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• 2019

스마트팩토리는 정보통신기술(ICT)를 이용한 공정의 모든 데이터를 수집, 분석하여 제어하고 있다. 기존보다 방대한 양의 데이터를 처리하기 위해 기업들은 하둡을 이용한다. 다양한 크기의 데이터가 나타나는 환경에서 HDFS을 효율적으로 관리하기 위한 적응형 캐시 관리 기법을 제안한다. 제안하는 기법은 데이터 노드의 로컬 디스크의 공간 이용 효율성을 높이고 평균 데이터 크기를 분석하여 데이터 노드 확장시 적합한 블록 크기를 적용할 수 있게 관리한다. 성능 평가를 통해 제안하는 기법의 데이터 노드에서 로컬 디스크 효율 향상과 읽기와 쓰기 속도의 속도에 효과를 보인다.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.7
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• pp.369-376
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• 2002

Although LRU is not adequate for database that has non-uniform reference pattern, it has been adopted in most database systems due to the absence of the proper alternative. We analyze database block reference pattern with the realistic database trace. Based on this analysis, we propose a new cache replacement policy. Trace analysis shows that extremely non-popular blocks take up about 70 % of the entire blocks. The influence of recency on blocks' re-reference likelihood is at first strong due to temporal locality, however, it rapidly decreases and eventually becomes negligible as stack distance increases. Based on this observation, RCB(Reference Characteristic Based) cache replacement policy, which we propose in this paper, classifies the entire blocks into four block groups by blocks' recency and re-reference likelihood, and operates different priority evaluation methods for each block group. RCB policy evicts non-popular blocks more quickly than the others and evaluates the priority of the block by frequency that has not been referenced for a long time. In a trace-driven simulation, RCB delivers a better performance than the existing polices(LRU, 2Q, LRU-K, LRFU). Especially compared to LRU. It reduces miss count by 5~l2.7%. Time complexity of RCB is O(1), which is the same with LRU and 2Q and superior to LRU-K(O(log$_2$N)) and LRFU(O(l) ~ O(log$_2$N)).

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.2
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• pp.39-49
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• 2019

Recently, CPU-GPU integrated heterogeneous multicore processors have been widely used for improving the performance of computing systems. Heterogeneous multicore processors integrate CPUs and GPUs on a single chip where CPUs and GPUs share the LLC(Last Level Cache). This causes a serious cache contention problem inside the processor, resulting in significant performance degradation. In this paper, we propose the partitioned LLC architecture to solve the cache contention problem in heterogeneous multicore processors. We analyze the performance impact varying the LLC size of CPUs and GPUs, respectively. According to our simulation results, the bigger the LLC size of the CPU, the CPU performance improves by up to 21%. However, the GPU shows negligible performance difference when the assigned LLC size increases. In other words, the GPU is less likely to lose the performance when the LLC size decreases. Because the performance degradation due to the LLC size reduction in GPU is much smaller than the performance improvement due to the increase of the LLC size of the CPU, the overall performance of heterogeneous multicore processors is expected to be improved by applying partitioned LLC to CPUs and GPUs. In addition, if we develop a memory management technique that can maximize the performance of each core in the future, we can greatly improve the performance of heterogeneous multicore processors.