• ETRI Journal
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• v.28 no.3
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• pp.397-400
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• 2006

The multi-layer advanced high-performance bus (ML-AHB) BusMatrix proposed by ARM is an excellent architecture for applying embedded systems with low power. However, there is one clock cycle delay for each master in the ML-AHB BusMatrix of the advanced microcontroller bus architecture (AMBA) design kit (ADK) whenever a master starts new transactions or changes the slave layers. In this letter, we propose an improved design method to remove the one clock cycle delay in the ML-AHB BusMatrix of an ADK. We also remarkably reduce the total area and power consumption of the ML-AHB BusMatrix of an ADK with the elimination of the heavy input stages.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.12
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• pp.435-440
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• 1983

The methods of forming the bus impedance matrix, which is mainly employed in fault analysis of power system, can be generally classified in catagories, (1) the one being the inverse matrix of bus admittance matrix, and (2) the other the bus impedance matrix succesive formation method by particular algorithms. The former method is theouetically elegant, but the formation and inverse of complex bus admittance matrix for large power system requires too much amounts of computer memory space and computing time. The latter method also requires too much memory space. Therefore, in this paper, an algorithm and computer program is introduced for the formation of a sparse bus impedance matrix which generates only the matching terms of the admittance matrix. So, this method can reduce the computer memory and computing time, and can be applied to fault analysis of large power system by small digital computer.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.11_12
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• pp.629-638
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• 2005

In the System on a Chip design, the on chip bus is one of the critical factors that decides the overall system performance. Especially, in the case or reusing the IPs such as processors, DSPs and multimedia IPs that requires higher bandwidth, the bandwidth problems of on chip bus are getting more serious. Recently ARM proposes the Multi-Layer AHB BusMatrix that is a highly efficient on chip bus to solve the bandwidth problems. The Multi-Layer AHB BusMatrix allows parallel access paths between multiple masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. However, there is one clock cycle delay for each master in existing Multi-Layer AHB BusMatrix whenever the master starts new transactions or changes the slave layers because of the Input Stage and arbitration logic realized with Moore type. In this paper, we improved the existing Multi-Layer AHB BusMatrix architecture to solve the one clock cycle delay problems and to reduce the area overhead of the Input Stage. With the elimination of the Input Stage and some restrictions on the arbitration scheme, we tan take away the one clock cycle delay and reduce the area overhead. Experimental results show that the end time of total bus transaction and the average latency time of improved Multi-Layer AHB BusMatrix are improved by $20\%\;and\;24\%$ respectively. in ease of executing a number of transactions by 4-beat incrementing burst type. Besides the total area and the clock period are reduced by $22\%\;and\;29\%$ respectively, compared with existing Multi-layer AHB BusMatrix.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.9
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• pp.1081-1087
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• 1999

Load Flow calulation methods can usually be divided into Gauss-Seidel method, Newton-Raphson method and decoupled method. Load flow calculation is a basic on-line or off-line process for power system planning. operation, control and state analysis. These days Newton-Raphson method is mainly used since it shows remarkable convergence characteristics. It, however, needs considerable calculation time in construction and calculation of inverse Jacobian matrix. In addition to that, Newton-Raphson method tends to fail to converge when system loading is heavy and system has a large R/X ratio. In this paper, matrix equation is used to make algebraic expression and then to slove load flow equation and to modify above defects. And it preserve P-Q bus part of Jacobian matrix to shorten computing time. Application of mentioned algorithm to 14 bus, 39 bus, 118 bus systems led to identical results and the same numbers of iteration obtained by Newton-Raphson method. The effect of computing time reduction showed about 28% , 30% , at each case of 39 bus, 118 bus system.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.41 no.5
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• pp.459-467
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• 1992

This paper presents a new algorithm for the countermeasure to alleviate the line overloads due to contingency without shedding loads in a power system. This method for relieving the line overloads by line switching is based on obtaining the kine outage distribution factors-the linear sensitivity factors, which give the amount of change in the power flow of each line due to the removal of a line in a power system. There factors are made up of the elements of sparse bus reactance matrix and brach reactances. In this paper a fast algorithm and program is presented for obtaining only the required bus reactance elements which corresponds to a non-zero elements of bus admittance matrix, and elements of columns which correspond to two terminal buses of the overloaded(monitored) line. The proposed algorithm has been validated in tests on a 6-bus and the 30-bus test system.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.311-315
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• 1998

Load Flow calculation methods can usually be divided into Gauss-Seidel method, Newton-Raphson method and decoupled method. Load flow calculation is a basic on-line or off-line process for power system planning, operation, control and state analysis. These days Newton-Raphson method is mainly used since it shows remarkable convergence characteristics. It, however, needs considerable calculation time in construction and calculation of inverse Jacobian matrix. In addition to that, Newton-Raphson method tends to fail to converge when system loading is heavy and system has a large R/X ratio. In this paper, matrix equation is used to make algebraic expression and then to solve load flow equation and to modify above defects. And it preserve certain part of Jacobian matrix to shorten the time of calculation. Application of mentioned algorithm to 14 bus, 39 bus, 118 bus systems led to identical result and the number of iteration got by Newton-Raphson method. The effect of time reduction showed about 28%, 30%, at each case of 39 bus, 118 bus system.

• Proceedings of the KIEE Conference
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• 1989.07a
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• pp.216-220
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• 1989

Direct calculation algorithm for the elements of A matrix is suggested for a single machine connected to the infinite bus. Excitation system and power system stabilizer are included. When A matrix is partitioned into seven submatrices, we can identify the location of non-zero elements and formula for each element. No matrix inversion and multiplication are necessary.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• Proceedings of the KIEE Conference
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• 1998.07c
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• pp.918-922
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• 1998

With the development of industry, the qualitical advancement of power is needed. Since it is placed in the end step of power system, the fault at the distribution system causes some users blackout directly. So if the fault occurs, quick restoration is very important subject and, for the reason, induction of the distribution automation system is now being progressed briskly. For the quick restoration of the faulted distribution system, the load shedding of the blackout-area must be followed, and the other problems like the shedded load, faulted voltage and the rest may cause other accident. Accordingly load shedding must be based on the precise calculation technique during the distribution system load flow(dist flow) calculation. In these days because of its superior convergence characteristic the Newton-Raphson method is most widely used. The number of buses in the distribution system amounts to thousands, and if the fault occurs at the distribution system, the speed for the dist flow calculation is to be improved to apply to the On-Line system. However, Newton-Raphson method takes much time relatively because it must calculate the Jacobian matrix and inverse matrix at every iteration, and in the case of huge load, the equation is hard to converge. In this thesis. matrix equation is used to make algebraical expression and then to solve load flow equation and to modify above defects. Then the complex matrix is divided into real part and imaginary part to keep sparcity. As a result time needed for calculation diminished. Application of mentioned algorithm to 302 bus, 700 bus, 1004 bus system led to almost identical result got by Newton-Raphson method and showed constant convergence characteristic. The effect of time reduction showed 88.2%, 86.4%, 85.1% at each case of 302 bus, 700 bus system 86.4%, and 1004 bus system.

• Proceedings of the KIEE Conference
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• 1993.11a
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• pp.6-8
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• 1993

Short Circuit analysis is one of the most fundamental procedures for power system analysis problem. In order 10 solve the problem, In order to solve the problem, it's required to develop an advanced algorithm by which modified bus admittance matrix are easily computed for a large number of alternative network configuration. This paper proposes a new calculation method to efficiently modify the bus impedance matrix elements of large power system by method for removal of link, and presents its Practicality by applying the proposed method in the power system model.