• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.499-502
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• 1999

This paper presents a PCI (Peripheral Component Interconnect) controller embedded in a multimedia processor, called FLOVA (FLOating point VLIW Architecture), targeting for 3D graphics applications. Fast I/O interfaces are essential for multimedia processors which usually handle large amount of multimedia data. Therefore, in FLOVA, PCI bus is adopted for I/O interface due to fast burst transaction. However, there are several problems in implementation and verification to use burst transaction of PCI. It is difficult to handle data transaction between two units which have two different operating frequency. FLOVA has more higher operating frequency about 100MHz than that of PCI local bus and it makes lower utilization of FLOVA bus. Also, traditional simulation is not sufficient for verification of PCI functionality. In this paper, we propose buffering schemes to implement the PCI controller with wide bandwidth and high bus utilization. Also, this paper shows how to verify the PCI controller using real PCI bus environments before its fabrication.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.169-171
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• 1996

In this paper, we have developed bus load forecasting system (BUSLOF) based on Windows 95. It has been developed for the secure operation of electric power system. It forecasts regional load and bus load using regional distribution factor(RDF) and bus distribution factor (BDF) which are calculated from bus load in the past. It is equipped with graphic user interface(GUI) which enables a user to easily access to the system. The performance of the developed system is estimated in sample data.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.259-266
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• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of KIBIM
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• v.8 no.3
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• pp.12-19
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• 2018

The research aims to find implications of machine learning and urban big data as a way to construct the flexible transportation network system of smart city by responding the urban context changes. This research deals with a problem that existing a bus headway model is difficult to respond urban situations in real-time. Therefore, utilizing the urban big data and machine learning prototyping tool in weathers, traffics, and bus statues, this research presents a flexible headway model to predict bus delay and analyze the result. The prototyping model is composed by real-time data of buses. The data is gathered through public data portals and real time Application Program Interface (API) by the government. These data are fundamental resources to organize interval pattern models of bus operations as traffic environment factors (road speeds, station conditions, weathers, and bus information of operating in real-time). The prototyping model is implemented by the machine learning tool (RapidMiner Studio) and conducted several tests for bus delays prediction according to specific circumstances. As a result, possibilities of transportation system are discussed for promoting the urban efficiency and the citizens' convenience by responding to urban conditions.

• Bulletin of the Korean Space Science Society
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• 2009.10a
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• pp.46.3-46.3
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• 2009

The SAR (Synthetic Aperture Radar) satellite has the advantage of implementing the imaging mission even though it is night time, cloudy weather, and all weather conditions, which is different from the satellite with the optical payload. This is the reason why the SAR satellite comes into the spotlight in the observation satellite field. The Korea Aerospace Research Institute (KARI) has been developing the first Korean SAR satellite and is currently integrating and testing the Flight Model. For the launch vehicle service, KARI finalized the selection of the launch vehicle service provider and finished Critical Design Review (CDR) of the interface between the bus and the launch vehicle. KARI and launch vehicle service provider also finished the test of the telemetry interface between the bus and the launch vehicle. The test of the telemetry interface has the purpose of checking the interface of the telemetry which is the SOH(State-of-Health) of the satellite in an early launch stage. For this test, KARI has finished the development of the spacecraft simulator which is composed of the bus simulator to generate the analog telemetry and the launch vehicle simulator to gather the telemetry. In this research, the result of the hardware implementation and the software implementation for the spacecraft simulator were described. Finally the results of the launch vehicle telemetry MUX test which were performed at the launch vehicle provider's design office by using the spacecraft simulator were summarized. It is expected that this simulator will be used in the next test after the manufacture of the launch vehicle.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2005.05a
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• pp.283-287
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• 2005

In this paper, one general approach is proposed for the design of power system that can be applicable for next generation LEO satellite application. The power system consists of solar panels, battery, and power control and distribution unit(PCDU). The PCDU contains solar array modules, battery interface modules, low-voltage power distribution modules, high-voltage distribution modules, heater power distribution modules, on-board computer interface modules, and internal DC/DC converter modules. The PCDU plays roles of protection of battery against overcharge by active control of solar array generated power, distribution of unregulated electrical power via controlled outlets to bus and instrument units, distribution of regulated electrical power to selected bus and instrument units, and provision of status monitoring and telecommand interface allowing the system and ground operate the power system, evaluate its performance and initiate appropriate countermeasures in case of abnormal conditions. We review the functional schemes of the main constitutes of the PCDU such as the battery interface module, the auxiliary supply module, solar array regulators with maximum power point tracking(MPPT) technology, heater power distribution modules, spacecraft unit power distribution modules, and instrument power distribution module.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9A
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• pp.868-873
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• 2010

H.264/AVC video compression standard has been adopted for DMB, digital TV and various next generation broadcasting, communication and consumer electronics applications, and modern DVR system is also based on H.264/AVC standard. Although PC-based DVRs use PCI bus for main interface typically, H.264/AVC codec for SOCs use AHB bus for host interface. In this paper, we present an implementation of PCI to AHB interface module for H.264/AVC codec to efficiently communicate with a PC and experimental results.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.288-290
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• 2014

In this paper, Escape and BTA(Bus Turn Around) modes of master bridge IC are implemented, which supports MIPI(Mobile Industry Processor Interface) DSI(Display Serial Interface) standard. MIPI DSI master bridge IC sends RGB data and various commands to display module(slave) in order to test it. The Escape mode is designed to implement LPDT, ULPS and trigger message transmissions. The BTA mode is designed to obtain various status information from slave in reverse direction. Functional simulation results show that the designed Escape and BTA modes work correctly for various conditions defined in MIPI DSI standard.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4A
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• pp.345-349
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• 2005

In this paper, the enhanced ATA(AT Attachment Interface with Extension) interface that combines the price of ATA and intelligent operation of SCSI(Small Computer System Interface) is realized both performance and structure of general interface used to connect peripheral devices that are used in PC(Personal Computer). SCSI bus is for peripheral devices that have intelligent operation. It is excellent bus that has well-arranged command system and stable hardware structure. But is aspect of price this peripheral device has the difficulty in purchase because there is price difference more than two times compared with ATA peripheral device. Whereas, although ATA peripheral device had low performance in the early period, after the improvement its speed has almost etched to SCSI and its price is also excellent. In this paper, the enhanced interface structure to fulfill price and performance was suggested and materialized as the hardware using such two advantages.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.4 s.334
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• pp.9-18
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• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.