• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.568-573
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• 2002

In this paper, the Viterbi decoder containing new branch metrics of the squared Euclidean distance with multiple order phase differences is introduced in order to improve the bit error rate (BER) in the differential detection of the trellis-coded MDPSK-OFDM. The proposed Viterbi decoder is conceptually same as the Continuous multiple phase differential detection method that uses the branch metric with multiple phase differences. Also, we describe the Viterbi algorithm in order to use this branch metrics. Our study shows that such a Viterbi decoder improves BER performance without sacrificing bandwidth and power efficiency Also. the proposed algorithm ran be used in the single carrier modulation.

• Ocean and Polar Research
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• v.33 no.3
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• pp.235-253
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• 2011

The annual variation of mesozooplankton community in the Jangmok harbor of Jinhae Bay was studied in relation to environmental variables. Sampling was carried out weekly from January to December 2009. During the study periods, mesozooplankton community consisted of 44 taxa and the annual mean abundance was 8308 inds. $m^{-3}$. The maximum abundance was observed to be 50043 inds. $m^{-3}$ in August and the minimum in April with 1013 inds. $m^{-3}$. Of these, Penilia avirostris, cirripedia larvae, Evadne tergestina, Acartia omorii, Oikopleura s, Paracalanus parvus s. l., Eurytemora pacifica, Podon s, Oithona s, and Acartia steueri were observed as dominant species in Jangmok bay and they also contributed to 79% of total mesozooplankton. According to non-metric multidimensional scaling (nMDS) and cluster analysis based on the mesozooplankton community data from each season, the community was divided into three groups. The first group included appearence species in winter and spring season, which is mainly dominated the copepod such as A. omorii and E. pacifica. The second and third group was composed with observed species in summer and autumn, respectively. Based on the SIMPER (similarity percentages), P. avirostris in summer and cirripedia larvae in autumn were significantly dominated. Our results indicate that although the mesozooplankton abundances in Jangmok harbor fluctuated abruptly, its annual variation was strongly influenced by water temperature.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.9C
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• pp.891-897
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• 2003

Partial response maxim likelihood (PRML) is a powerful and indispensable detection scheme for perpendicular magnetic recording channels. The performance of PRML can be improved by incorporating a noise prediction scheme into branch metric computations of Viterbi algorithm (VA). However, the systems constructed by VA have shortcomings in the form of high complexity and cost. In this connection, a new simple detection scheme is proposed by exploiting the minimum run-length parameter d=1 of RLL code. The proposed detection scheme have a slicer instead of Viterbi detector and a noise predictor as a feedback filter. Therefore, to improve BER performance, the proposed detection scheme is extended to dual detection scheme for improving the BER performance. Simulation results show that the proposed scheme has a comparable performance to noise-predictive maximum likelihood (NPML) detector with less complexity when the partial response (PR) target is (1,2,1).

• Journal of IKEEE
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• v.24 no.3
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• pp.838-844
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• 2020

In this paper, we propose an efficient Viterbi processor using Joint Viterbi detection and decoding (JVDD) algorithm for a for bluetooth low energy (BLE) system. Since the convolutional coded Gaussian minimum-shift keying (GMSK) signal is specified in the BLE 5.0 standard, two Viterbi processors are needed for detection and decoding. However, the proposed JVDD scheme uses only one Viterbi processor by modifying the branch metric with inter-symbol interference information from GMSK modulation; therefore, the hardware complexity can be significantly reduced without performance degradation. Low-latency and low-complexity hardware architecture for the proposed JVDD algorithm was proposed, which makes Viterbi decoding completed within one clock cycle. Viterbi Processor RTL synthesis results on a GF55nm process show that the gate count is 12K and the memory unit and the initial latency is reduced by 33% compared to the modified state exchange (MSE).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1734-1745
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• 1996

In this paper, a modified fixed-delay tree search with decision feedback(FDTS/DF) for compensation of non-linear distortion in digital magnetic recording channels is discussed. Since the nonlinear distortion, which becomes significant as recording density increases, is generally well modeled by the discrete Volterra series, the proposed equlizer is composed of a nolinear feedforward filter, a linear feedback filter, and a nonlinear distorton table, the values of which are determined by considering the effect of nonlinear distortion due to future data as well as the previous and current one. At the decision stage of FDTS, a path minimizing the branch metric is chosen by using the previously detected values, current predicted value, and future predicted value. We compare the performance of the linear FDTS/DF, the previous nonlinear FDTS/DF, and the proposed nonlinear FDTS/DF by computer simulation, and confirm that the proposed one chieves the best performance at high-density recording.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.546-552
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• 2000

The decoding of Turbo-Code relies on the application of a soft input/soft output decoders which can be realized using maximum-a-posteriori(MAP) symbol estimator[l]. Radix-2 MAP decoder can not be used for high speed communications because of a large number of interleaver block size N. This paper proposed a new simple method for radix-4 MAP decoder based on radix-2 MAP decoder in order to reduce the interleave block size. A branch metrics, forward and backward recursive functions are proposed for applying to radix-4 MAP structure with symbol interleaver. Radix-4 MAP decoder shall be illustratively described and its error performance capability shall be compared to conventional radix-2 MAP decoder in AWGN channel.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1999.11b
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• pp.173-178
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• 1999

The Trellis Coded Modulation(TCM) allows the considerable achievements of coding gains compare with conventional multi-level modulation without compromising bandwidth efficiency. In this paper, we are presented a design of the parallel Viterbi decoder for 16-QAM TCM decoder with large constraint length (K=9), which can be applicable for the Digital Audio Broadcasting(DAB) receiver. As a mid-term result, a parallel Branch Metric Calculator (BMC)can compute 16 BMs within 3 clocks and a parallel 16 Add-Compare-Selects (ACS) unit can compute in a single clock. And also, two 256 Path Metric Memories (PMM) 32 Trace Back(TB) memories are specially designed with shuffle exchange switches for 16 parallel accesses. As a VHDL simulation, we can find the correctness of proposed model, which can be operated 16 S per symbol. Now, we are performing the hardware reduction for realtime operation and FPGA implementation.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.2 s.332
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• pp.61-74
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• 2005

Digital Multimedia Broadcasting(DMB) is a reliable multi-service system for reception by mobile and portable receivers. DMB system allows interference-free reception under the conditions of multipath propagation and transmission errors using COFDM modulation scheme, simultaneously, needs powerful channel error's correction ability. Viterbi Decoder for DMB receiver uses punctured convolutional code and needs lots of computations for real-time operation. So, it is desired to design a high speed and low-power hardware scheme for Viterbi decoder. This paper proposes a combined add-compare-select(ACS) and path metric normalization(PMN) unit for computation power. The proposed PMN architecture reduces the problem of the critical path by applying fixed value for selection algorithm due to the comparison tree which has a weak point from structure with the high-speed operation. The proposed ACS uses the decomposition and the pre-computation technique for reducing the complicated degree of the adder, the comparator and multiplexer. According to a simulation result, reduction of area $3.78\%$, power consumption $12.22\%$, maximum gate delay $23.80\%$ occurred from punctured viterbi decoder for DMB system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4A
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• pp.539-545
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• 2000

A 40-Mb/s, 64-state, R= 1/2, 3 bit soft decision Viterbi decoder based on Radix-4 method has been designed and fabricated using a FLEX10K CPLD chip in this paper. In order to implement the high-speed Viterbi decoder, the architectures of adder-compare-select(ACS), branch metric calculation(BMC), trace back(TB) are present. In practical designed by ASIC, the speed is faster than that of CPLD by 6~7 times. Therefore, 40 Mb/s Viterbi decoder architecture can be used for high-speed wireless multimedia communications with 200 Mb/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.426-432
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• 2007

The MAP algorithm is designed and implemented through the sliding window method for turbo decoding. First, the implementation issues, which are the length of the sliding window and the normalization method of state metrics are reviewed, and their optimal values are obtained by the simulation. All component schemes of the decoder including the branch metric evaluator are also presented. The proposed MAP architecture can be easily redesigned according to the size of sliding window, that is, sub-frame length because of its simplicity on buffer control.