• Title/Summary/Keyword: bottleneck structure

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Thermal Characteristics of a Heat Sink with Bypass Structure for GaN-based Laser Diode (열 우회 구조를 적용한 GaN 레이저 다이오드 패키지의 열특성 분석)

  • Ji, Byeong-Gwan;Lee, Seung-Gol;Park, Se-Geun;O, Beom-Hoan
    • Korean Journal of Optics and Photonics
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    • v.27 no.6
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    • pp.218-222
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    • 2016
  • The thermal characteristics of a laser diode TO package has been analyzed using a commercial computational fluid dynamics (CFD) tool, and the thermal bypass structure was optimized. Comparison of device temperature and the estimated thermal resistance of the resultant structure showed that the bypass structure relieved the thermal bottleneck, and improved the thermal characteristics quite efficiently.

Fluctuation in Plasma Nanofabrication

  • Shiratani, Masaharu
    • Proceedings of the Korean Vacuum Society Conference
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    • 2016.02a
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    • pp.96-96
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    • 2016
  • Nanotechnology mostly employs nano-materials and nano-structures with distinctive properties based on their size, structure, and composition. It is quite difficult to produce nano-materials and nano-structures with identical sizes, structures, and compositions in large quantities, because of spatiotemporal fluctuation of production processes. In other words, fluctuation is the bottleneck in nanotechnology. We propose three strategies to suppress such fluctuations: employing 1) difference between linear and nonlinear phenomena, 2) difference in time constants, and 3) nucleation as a bottleneck phenomenon. We are also developing nano- and micro-scale guided assembly using plasmas as a plasma nanofabrication.1-5) We manipulate nano- and micro-objects using electrostatic, electromagnetic, ion drag, neutral drag, and optical forces. The accuracy of positioning the objects depends on fluctuation of position and energy of an object in plasmas. Here we evaluate such fluctuations and discuss the mechanism behind them. We conducted in-situ evaluation of local plasma potential fluctuation using tracking analysis of fine particles (=objects) in plasmas. Experiments were carried out with a radio frequency low-pressure plasma reactor, where we set two quartz windows at the top and bottom of the reactor. Ar plasmas were generated at 200 Pa by applying 13.56MHz, 450V peak-to-peak voltage. The injected fine particles were monodisperse methyl methacrylate-polymer spheres of $10{\mu}m$ in diameter. Fine particles were injected into the reactor and were suspended around the plasma/sheath boundary near the powered electrode. We observed binary collision of fine particles with a high-speed camera. The frame rate was 1000-10000 fps. Time evolution of their distance from the center of mass was measured by tracking analysis of the two particles. Kinetic energy during the collision was obtained from the result. Potential energy formed between the two particles was deduced by assuming the potential energy plus the kinetic energy is constant. The interaction potential is fluctuated during the collision. Maximum amplitude of the fluctuation is 25eV, and the average is 8eV. The fluctuation can be caused by neutral molecule collisions, ion collisions, and fluctuation of electrostatic force. Among theses possible causes, fluctuation of electrostatic force may be main one, because the fine particle has a large negative charge of -17000e and the corresponding electrostatic force is large compared to other forces.

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Design of a scalable general-purpose parallel associative processor using content-addressable memory (Content-Addressable Memory를 이용한 확장 가능한 범용 병렬 Associative Processor 설계)

  • Park, Tae-Geun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.2 s.344
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    • pp.51-59
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    • 2006
  • Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.

An Application Method and Effect Analysis of the DBR(Drum-Buffer-Rope) Method Under the Re-entrant Process (재투입공정 하에서 DBR 기법 적용 방안 및 효과분석)

  • Yang, Hyunjun;Jeong, Sukjae;Yoon, SungWook
    • Journal of the Korea Society for Simulation
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    • v.29 no.1
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    • pp.57-69
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    • 2020
  • Many researchers have recommended that DBR scheduling would be an efficient method to maintain the balance of their workload among many processes in the general flow shop. However, as product variety has increased in recent years, the process has become more complex and requires the re-entrance of raw materials and work in process. The re-entrant line has known for the complex manufacturing process that raw materials are repeatedly processed on the same machine. This study reviews the applicability of DBR against the re-entrant manufacturing line due to the distinguishing characteristics and the higher complexity caused by multiple visits of a job into the identical process. In order to apply the DBR method to the re-entrant process, the main idea is to reconstruct re-entrant process into a virtual flow process(loop) that has a single bottleneck. This study discusses the following two questions. First, DBR is also superior to traditional scheduling methods against re-entrant manufacturing line. And how we structure and detect the system bottleneck (or sub-bottleneck) through drum-buffer-rope concepts. To answer the above questions, we experimented and analyzed the effects of the applicability of DBR under the general re-entrant process model(TRC, Technology Research Center). As a result, we have identified a balance between loops for cycle time and work in process.

Dynamic data Path Prediction in Network Virtual Environment

  • Jeoung, You-Sun;Ra, Sang-Dong
    • Journal of information and communication convergence engineering
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    • v.5 no.2
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    • pp.83-87
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    • 2007
  • This research studies real time interaction and dynamic data shared through 3D scenes in virtual network environments. In a distributed virtual environment of client-server structure, consistency is maintained by the static information exchange; as jerks occur by packet delay when updating messages of dynamic data exchanges are broadcasted disorderly, the network bottleneck is reduced by predicting the movement path by using the Dead-reckoning algorithm. In Dead-reckoning path prediction, the error between the estimated and the actual static values which is over the threshold based on the shared object location requires interpolation and multicasting of the previous location by the ESPDU of DIS. The shared dynamic data of the 3D virtual environment is implementation using the VRML.

Class 4 Active RFID Multi-hop Relay System based on IEEE 802.15.4a Low-Rate UWB in Sensor Network

  • Zhang, Hong;Hong, Sung-Hyun;Chang, Kyung-Hi
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.4 no.3
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    • pp.258-272
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    • 2010
  • The low-rate (LR) UWB is a promising technology for the ubiquitous sensor network (USN) due to its extremely low power consumption and simple transceiver implementation. However the limited communication range is a bottleneck for its widespread use. This paper deals with a new frame structure of class 4 active RFID multi-hop relay system based on ISO/IEC 18000-7 standard integrating with IEEE 802.15.4a LR-UWB PHY layer specification, which sets up a connection to USN. As a result of the vital importance of the coverage and throughput in the application of USN, further we analyze the performance of the proposed system considered both impulse radio UWB (IR-UWB) and chirp spread spectrum (CSS). Our simulation results show that the coverage and throughput are remarkably increased.

Determination of Design Parameters for Automobile Parts Recycling (자동차 부품의 재활용을 위한 설계시의 주요인자 결정)

  • 목학수;문광섭;박홍석;성재현;최흥원
    • Journal of the Korean Society for Precision Engineering
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    • v.20 no.1
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    • pp.159-171
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    • 2003
  • In this paper, same parts of a domestic automobiles and foreign automobiles are disassembled fur the evaluation of disassemblability, especially door trim and bumper. Influencing factors of disassembly are determined by the classification of bottleneck process in disassembly process. On the bases of disassembly sequence and structure of parts and subassembly, disassemblability is classified into aye categories. The influencing factors, which are related with the five categories are determined. By these relations, the checklist for disassembly evaluation is draw up and score tables of checked factors are established. For the establishing the disassembly score tables, the weighting values of each five categories are calculated by the disassembly test of automobiles and then, the weighting values of each influencing factors of five categories are calculated by the method of AHP (Analytic Hierarchy Process). And the last, the weighting values are modified and recalculated from the disassembly test. Using these weighting values, the score of influencing factors are determined and then, the score tables are established based on the score of influencing factors.

A real-time high speed full search block matching motion estimation processor (고속 실시간 처리 full search block matching 움직임 추정 프로세서)

  • 유재희;김준호
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.12
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    • pp.110-119
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    • 1996
  • A novel high speed VLSI architecture and its VLSI realization methodologies for a motion estimation processor based on full search block matching algorithm are presentd. The presented architecture is designed in order to be suitable for highly parallel and pipelined processing with identical PE's and adjustable in performance and hardware amount according to various application areas. Also, the throughput is maximized by enhancing PE utilization up to 100% and the chip pin count is reduced by reusing image data with embedded image memories. Also, the uniform and identical data processing structure of PE's eases VLSI implementation and the clock rate of external I/O data can be made slower compared to internal clock rate to resolve I/O bottleneck problem. The logic and spice simulation results of the proposed architecture are presented. The performances of the proposed architecture are evaluated and compared with other architectures. Finally, the chip layout is shown.

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Performance Comparison of Deep Feature Based Speaker Verification Systems (깊은 신경망 특징 기반 화자 검증 시스템의 성능 비교)

  • Kim, Dae Hyun;Seong, Woo Kyeong;Kim, Hong Kook
    • Phonetics and Speech Sciences
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    • v.7 no.4
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    • pp.9-16
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    • 2015
  • In this paper, several experiments are performed according to deep neural network (DNN) based features for the performance comparison of speaker verification (SV) systems. To this end, input features for a DNN, such as mel-frequency cepstral coefficient (MFCC), linear-frequency cepstral coefficient (LFCC), and perceptual linear prediction (PLP), are first compared in a view of the SV performance. After that, the effect of a DNN training method and a structure of hidden layers of DNNs on the SV performance is investigated depending on the type of features. The performance of an SV system is then evaluated on the basis of I-vector or probabilistic linear discriminant analysis (PLDA) scoring method. It is shown from SV experiments that a tandem feature of DNN bottleneck feature and MFCC feature gives the best performance when DNNs are configured using a rectangular type of hidden layers and trained with a supervised training method.

Adaptive ridge procedure for L0-penalized weighted support vector machines

  • Kim, Kyoung Hee;Shin, Seung Jun
    • Journal of the Korean Data and Information Science Society
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    • v.28 no.6
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    • pp.1271-1278
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    • 2017
  • Although the $L_0$-penalty is the most natural choice to identify the sparsity structure of the model, it has not been widely used due to the computational bottleneck. Recently, the adaptive ridge procedure is developed to efficiently approximate a $L_q$-penalized problem to an iterative $L_2$-penalized one. In this article, we proposed to apply the adaptive ridge procedure to solve the $L_0$-penalized weighted support vector machine (WSVM) to facilitate the corresponding optimization. Our numerical investigation shows the advantageous performance of the $L_0$-penalized WSVM compared to the conventional WSVM with $L_2$ penalty for both simulated and real data sets.