• Journal of the Microelectronics and Packaging Society
• /
• v.26 no.4
• /
• pp.7-13
• /
• 2019

Power module is getting attention from electronic industries such as solar cell, battery and electric vehicles. Transient liquid phase (TLP) boding, sintering with Ag and Cu powders and wire bonding are applied to power module packaging. Sintering is a popular process but it has some disadvantages such as high cost, complex procedures and long bonding time. Meanwhile, TLP bonding has lower bonding temperature, cost effectiveness and less porosity. However, it also needs to improve ductility of the intermetallic compounds (IMCs) at the joint. Wire boding is also an important interconnection process between semiconductor chip and metal lead for direct bonded copper (DBC). In this study, TLP bonding using Sn-based solders and wire bonding process for power electronics packaging are described.

• Transactions of Materials Processing
• /
• v.15 no.6 s.87
• /
• pp.421-427
• /
• 2006

Drawing process of Al-1%Si bonding wire considering fine Si particle is analyzed in this study using FE-simulation. Al-1%Si boding wire requires electric conductivity because Al-1%Si bonding wire is used for interconnection in semiconductor device. About 1% of Si is added to Al wire for dispersion-strengthening. Distribution and shape of fine Si particle have strongly influence on the wire drawing process. In this study, therefore, the finite-element model based on the observation of wire by continuous casting is used to analyze the effect of various parameters, such as the reduction in area, the semi-die angle, the aspect ratio, the inter-particle spacing and orientation angle of the fine Si particle on wire drawing processes. The effect of each parameter on the wire drawing process is investigated from the aspect of ductility and defects of wire. From the results of the analysis, it is possible to obtain the important basic data which can be guaranteed in the fracture prevention of Al-1 %Si wire.

• ETRI Journal
• /
• v.38 no.1
• /
• pp.133-140
• /
• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.