• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.2
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• pp.43-51
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• 1997

In this paper, we quantize the image data to simplify the systolic array architecture for block matching algorithm. As the number of bits for pixel data to be processed is reduced by quantization, one can simplify the hardware of systolic array. Especially, if the bit serial input is used, one can even more simplify the structure of processing element. First, we analize the effect of quantization to a block matching. then we show the structure of quantizer and processing element when bit serial input is used. The simulation results applied to standard images have shown that the proposed block matching method has less prediction error than the conventional high speed algorithm.

• The Transactions of the Korea Information Processing Society
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• v.6 no.11S
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• pp.3278-3288
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• 1999

This paper proposes a security platform, called SCAP(Security platform for CORBA based APplication), to cope with potential threats in a distributed object system. SCAP supports CORBA security specification announced by OMG. SCAP is comprised of four functional blocks, which co-work with ORB to provide security services: Authentication Block, Association Block, Access Control Block, and Security Information Management Block. It is designed to support Common Secure Interoperability Functionality Level 2, which is useful for large-scale intra-, or inter-network based applications. Actual security services, which are dependent on supporting security technology, will be provided as external security service for replace ability. Implementation issues such as how to simulate an interceptor mechanism using a commercial ORB product without source code, and how to extend Current object required for security services are also described. At the end of the paper, the SCAP applied to the web environment is described to show its practical utilization.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.177-180
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• 2001

This paper presents a new fast motion estimation algorithm for video coding. This method classifies blocks in a frame into moving blocks and background blocks, and then searches the best-matched blocks for only moving blocks. Experimental results show the effectiveness of the proposed method.

• International Journal of Advanced Culture Technology
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• v.10 no.2
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• pp.233-239
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• 2022

Recently, research is being conducted on the rapid service provision and reliability of the instance-based rather than the existing IP-based structure. Research is mainly conducted through Block cloud, a platform that combines service-centric networking (SCN) and blockchain. In addition, the Internet of Things network has been proposed as a fog computing environment in the structure of the existing cloud computing. Fog computing is an environment suitable for real-time information processing. In this paper, we propose a new Internet network structure based on fog computing that requires real-time for rapid processing of IoT services. The proposed system applies IoTA, the third-generation blockchain based on DAG, to the block cloud. In addition, we want to propose a basic model of the object block chain and check the application services of electric vehicles.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.05a
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• pp.517-518
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• 2023

최근 뇌-컴퓨터 인터페이스 분야에서는 뇌파 신호를 이용한 운동 심상 분류 연구가 활발히 이루어지고 있다. 뇌파는 개인별 차이가 큰 생체 신호로, 사용자에 독립적인 경우 추론이 어려워지는 문제가 있어 운동 심상 분류에서는 주로 피험자 종속적인 연구가 행해져 왔다. 본 논문에서는 컨볼루션 신경망 기반의 뇌파 분류 모델인 EEGNet 에 새로운 방식으로 개선한 Squeeze-and-Excitation block 을 적용해 피험자에 대해 독립적인 운동 심상 분류 성능을 향상시키는 방법을 제안하며, 제안한 Squeeze-and-Excitation block 을 적용한 모델이 기존 모델보다 높은 분류 성능을 보여주는 것을 실험적으로 확인하였다.

• Journal of Information Processing Systems
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• v.20 no.1
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• pp.24-37
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• 2024

To address the requirement for high-speed encryption of large amounts of data, this study improves the widely adopted cipher block chaining (CBC) mode and proposes a controllable parallel cipher block chaining (CPCBC) block cipher mode of operation. The mode consists of two phases: extension and parallel encryption. In the extension phase, the degree of parallelism n is determined as needed. In the parallel encryption phase, n cipher blocks generated in the expansion phase are used as the initialization vectors to open n parallel encryption chains for parallel encryption. The security analysis demonstrates that CPCBC mode can enhance the resistance to byte-flipping attacks and padding oracle attacks if parallelism n is kept secret. Security has been improved when compared to the traditional CBC mode. Performance analysis reveals that this scheme has an almost linear acceleration ratio in the case of encrypting a large amount of data. Compared with the conventional CBC mode, the encryption speed is significantly faster.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.179-185
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• 2019

This paper proposes a block-type classification based image binarization for the implementation of the low-power feature extraction algorithm. The proposed method can be implemented with threshold value re-use technique approach when the image divided into $64{\times}64$ macro blocks size and calculating the threshold value for each block type only once. The algorithm is validated based on quantitative results that only a threshold value change rate of up to 9% occurs within the same image/block type. Existing algorithms should compute the threshold value for 64 blocks when the macro block is divided by $64{\times}64$ on the basis of $512{\times}512$ images, but all suggestions can be made only once for best cases where the same block type is printed, and for the remaining 63 blocks, the adaptive threshold calculation can be reduced by only performing a block type classification process. The threshold calculation operation is performed five times when all block types occur, and only the block type separation process can be performed for the remaining 59 blocks, so 93% adaptive threshold calculation operation can be reduced.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.3
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• pp.23-32
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• 2008

The computing power of graphics processing units(GPU) has already surpassed that of CPU and the gap between their powers is getting wider. Thus, research on GPGPU which applies GPU to general purpose becomes popular and shows great success especially in the field of parallel data processing. Since the implementation of cryptographic algorithm using GPU was started by Cook et at. in 2005, improved results using graphic libraries such as OpenGL and DirectX have been published. In this paper, we present skills and results of implementing block ciphers using CUDA library announced by NVIDIA in 2007. Also, we discuss a general method converting source codes of block ciphers on CPU to those on GPU. On NVIDIA 8800GTX GPU, the resulting speeds of block cipher AES, ARIA, and DES are 4.5Gbps, 7.0Gbps, and 2.8Gbps, respectively which are faster than the those on CPU.

• Journal of Korea Multimedia Society
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• v.7 no.8
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• pp.1170-1182
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• 2004

A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed memory partitioning method to access pixel data from 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Experimental results show that the proposed architecture achieves a high performance for real time motion estimation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.