• Journal of the Institute of Electronics Engineers of Korea CI
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• v.40 no.6
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• pp.118-126
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• 2003

This paper presents a low-complexity algorithm lot browsing a HD bit stream in DTV PVR according to its characteristics and also presents its implementation results. We propose an efficient algorithm which detects shots using some information after decoding MPEG-2 data, clusters them into scene and episode, and intelligently browses them according to some criteria after calculating their complexity. Some simulation results are presented to show the performance feasibility of the proposed algorithm. To implement it in real time, we propose an efficient hybrid architecture which partitions the algorithm into two parts of hardware and software. The hardware covers decoding process and extraction of some basic information which take most complexity in implementing the algorithm. The software covers the heuristic part of tile algorithm which has low complexity and needs to be expandable.

• Journal of Broadcast Engineering
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• v.1 no.2
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• pp.152-164
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• 1996

This paper describes the hardware architecture and implementation trade-offs of the Grand Alliance HDTV video encoder system. The implemented video encoder accepts video in 1125 line(30Hz) interlaced format, and produces a bit-stream compliant with the motion picture experts group version 2(MPEG-2) standards. The encoder processing includes large- area motion estimation and an advanced rate control mechanism. To keep the system complexity realizable, we adopt a fast hierarchical motion estimation method and developed its hardware architecture. Furthermore an adaptive perceptual quantization method is adopted to improve the perceptual quality. The developed system Is based on the 4-way parallel processing architecture and is implemented by using programmable IC, memory IC, and special-purpose processors such as DCT and motion estimation processors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.3
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• pp.247-259
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• 1992

In this paper, the types of the data exchange between a cell site and a cobile phonefor the call processing on the AMPS(Advanced Mobile Phone Service) are investigated, and the circuit for processing the wideband data stream according to the data types is designed and implemented. The circuit for detecting the Busy / Idle bit which is needed for determining the channel access, the circuit for detecting the word sync and the circuit for transmitting and receiving the wideband data is designed. The 3-out-of-5 majority vote of the 5received data is performed to reduce error and an algorithm requiring a small buffer size for real time processing of voting process is proposed. The method to overcome the computational complexity and the real time constraint of the conventional BCH decoding is proposed.

• Journal of Korea Multimedia Society
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• v.14 no.1
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• pp.44-53
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• 2011

H.264/SVC provides scalable video streams which consist of a base layer and one or more enhancement layers. Thus, it can efficiently adapt encoded streams to individual network conditions by dropping some layers of bit streams. However, on a dynamic environment such as the Internet, random packet losses due to network congestion can cause drastic effect on SVC quality. To avoid network congestion, the rate of video streams should be adjusted by carefully selecting a layer of each stream. In this paper, we propose three layer selection algorithms which can avoid network congestion by using the rate-distortion characteristics of streams. Simulation results show that FS(Far-Sighted) algorithm can maximize the overall PSNR value of streams by efficiently using the characteristics of video streams.

• Journal of the Korea Computer Industry Society
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• v.2 no.8
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• pp.1075-1088
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• 2001

In this paper, we propose a method for dynamic selection of unrestricted motion vector(UMV) or default prediction mode(DPM) in H.263 bit stream. For this, we use the error of compensated image and the magnitude of motion vector. In the proposed strategy, the UMV mode is dynamically applied in a frame according to average magnitude of motion vector and error of compensated image. This scheme has improved the quality of image compared to the fixed mode UMV or DPM only. Number of searching points are greatly reduced when comparing to UMV The proposed method is more profitable to long video sequences having camera movement locally.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.26 no.2
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• pp.327-334
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• 2016

Contrary to the common belief, DRAM which is used for the main memory of various computing devices retains its content even though it is powered-off. Especially, the data-retaining time can increase if DRAM is cooled down. The Cold Boot Attack, a kind of side-channel attacks, tries to recover the sensitive information such as the cryptographic key from the powered-off DRAM. This paper proposes a new algorithm which recovers the AES key under the symmetric-decay cold-boot-attack model. In particular, the proposed algorithm uses the strategy of reducing the size of the candidate key space by testing the randomness of the extracted AES key bit stream.

• Journal of Internet Computing and Services
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• v.6 no.4
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• pp.103-114
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• 2005

In this paper, we propose a new trnascoding method for improving picture's visual quality when frames are skipped. the proposed method utilizes the relationships of motion vectors between successive frames, and 4 motion vectors a macroblock are considered in transcoding. Since the proposed method does not require any decoding process of encoded bit stream, the computational complexity for estimating motion vectors can be eliminated. Experimental results illustrated that as transcoded frames are getting far from I pictures and as the degree of motions in video sequences are getting higher, the picture quality by using our proposed method shows better performances than existing schemes.

• Journal of KIISE:Information Networking
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• v.34 no.3
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• pp.175-185
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• 2007

In IEEE 802.15.4 (Low-Rate Wireless Personal Area Network) specification, a successful reception and validation of a data or MAC command frame can be confirmed with an acknowledgment. However, the specification does not support security for acknowledgment frame; the lack of a MAC covering acknowledgments allows an adversary to forge an acknowledgment for any frame. This paper proposes an identity authentication mechanism at the link layer for acknowledgment frame in IEEE 802.15.4 network. With the proposed mechanism there is only three bits for authentication, which can greatly reduce overhead of device. The encrypted bit stream for identity authentication will be transmitted to device by coordinator within association process. Statistical method and simulation results prove that our mechanism is successful in handling MAC layer attack.

• Journal of Korea Multimedia Society
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• v.11 no.5
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• pp.588-596
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• 2008

For the patients' privacy, secure access control of medical images is essentially necessary. In this paper, two types of Region of Interest (ROI)-based selective encryption schemes are proposed, which concentrate on the security of crucial parts in medical images. The first scheme randomly inverts the most significant bits of ROI coefficients in several high frequency subbands in the transform domain, which only incurs little loss on compression efficiency. The second scheme employs a symmetric key encryption to encrypt selectively the ROI data in the final code-stream, which provides sufficient confidentiality. Both of two schemes are backward compatible so as to ensure a standard bitstream compliant decoder so the encrypted images can be reconstructed without any crash.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.