• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.107-115
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• 2014

The reduced-bit transform based bit-plane matching algorithm (BPM) can obtain the block matching result through its simple calculation and hardware design compared to the conventional block matching algorithms (BMAs), but the block matching accuracy of BPMs is somewhat low. In this paper, reduced-bit transform based sum of the absolute difference (R-SAD) is proposed to improve the block matching accuracy in comparison with the conventional BPMs and it is shown that the matching process can be obtained using the logical operations. Firstly, this method transforms the current and the reference images into their respective 2-bit images and then a truth table is obtained from the relation between input and output 2-bit images. Next, a truth table is simplified by Karnaugh map and the absolute difference is calculated by using simple logical operations. Finally, the simulation results show that the proposed R-SAD can obtain higher accuracy in block matching results compared to the conventional BPMs through the PSNR analysis in the motion compensation experiments.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.403-406
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• 1999

Among the compression methods of moving picture information, a motion estimation method is used to remove time-repeating. The Block Matching Algorithm in motion estimation methods is the commonest one. In recent days, it is required the more advanced high quality in many image processing fields, for example HDTV, etc. Therefore, we have to accomplish not by means of Partial Search Algorithm, but by means of Full Search Algorithm in Block Matching Algorithm. In this paper, it is suggested a structure that reduce total calculation quantity and size, because the structure using Bit Plane select and use only 3bit of 8bit luminance signal.

• Journal of KIISE:Software and Applications
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• v.27 no.5
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• pp.543-550
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• 2000

An adaptive bit-reduced mean absolute difference (ABRMAD) is presented as a criterion for the block-matching algorithm (BMA) to reduce the complexity of the VLSI Implementation and to improve the processing time. The ABRMAD uses the lower pixel resolution of the significant bits instead of full resolution pixel values to estimate the motion vector (MV) by examining the pixels Ina block. Simulation results show that the 4-bit ABRMAD has competitive mean square error (MSE)results and a half less hardware complexity than the MAD criterion, It has also better characteristics in terms of both MSE performance and hardware complexity than the Minimax criterion and has better MSE performance than the difference pixel counting(DPC), binary block-matching with edge-map(BBME), and bit-plane matching(BPM) with the same number of bits.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1471-1481
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• 1998

In this paper, we propose a new digital image stabilization scheme based on the bit-plane matching. In the proposed algorithm, the conventional motion estimation algorithms are applied to the binary images extracted from the bit-plane images. It is shown that the computational complexity of the proposed algorithm can be significantly reduced by replacing the arithmetic calculations with the binary Boolean functions, while the accuracy of motion estimation is maintained. Furthermore, an adaptive algorithm for selecting a bit-plane in consideration of changes in external illumination can provide the robustness of the proposed algorithm. We compared the proposed algorithm with existing algorithms using root mean square error (RMSE) on the basis of the brute-force method, and proved experimentally that the proposed method detects the camera motion more accurately than existing algorithms. In addition, the proposed algorithm performs digital image stabilization with less computation.

• The Journal of Information Technology
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• v.3 no.2
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• pp.39-47
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• 2000

Among the compression methods of moving picture information, a motion estimation method is used to remove time-repeating. The Block Matching Algorithm in motion estimation methods is the commonest one. In recent days, it is required the more advanced high quality in many image processing fields, for example HDTV, etc. Therefore, we have to accomplish not by means of Partial Search Algorithm, but by means of Full Search Algorithm in Block Matching Algorithm. In this paper, it is suggested a structure that reduce total calculation quantity and size, because the structure using Bit Plane select and use only 3bit of 8bit luminance signal.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.11a
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• pp.119-122
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• 1997

움직임 추정(motion estimation)은 압축 부호화나 영상 안정화 시스템, 비젼 시스템 등과 같은 동영상 처리에 있어서 핵심 기술 중의 하나이다. 그러나 기존의 전역 탐색(brute-force) 알고리즘과 같은 움직임 추정 기법은 방대한 양의 계산을 필요로 하기 때문에 처리 시간이 커지고, 하드웨어로 구현하였을 때 회로가 복잡해진다는 문제점을 안고 있다. 본 논문에서는 비트 플레인(bit-plane)에서의 정합을 이용하여 움직임을 추정하는 새로운 기법을 제안한다. 제안된 기법에서는 기존의 전역 탐색 알고리즘을 하나의 비트 플레인으로부터 추출한 이진 영상에 적용함으로써 움직임 추정에 소요되는 계산량을 크게 줄이면서도 우수한 움직임 추정 성능을 갖도록 하였다. 실험 부분에서는 동영상으로부터 카메라의 이동으로 인한 전역적인 움직임을 추정하는데 제안된 기법을 사용한 결과를 제시하였다. 특히 제안된 기법은 비트 플레인을 선정하는데 있어서 적응 기법을 적용하였기 때문에 조도 변화 등과 같은 열악한 환경에서도 안정적으로 동작한다는 것을 실험을 통하여 보였다.

• Journal of Broadcast Engineering
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• v.16 no.5
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• pp.861-872
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• 2011

Many fast block-matching algorithms (BMAs) in motion estimation field reduce computational complexity by screening the number of checking points. Although many fast BMAs reduce computations, sometimes they should endure matching errors in comparison with full-search algorithm (FSA). In this paper, a novel fast BMA for constrained one-bit transform (C1BT)-based motion estimation is proposed in order to decrease the calculations of the block distortion measure. Unlike the classical fast BMAs, the proposed algorithm shows a new approach to reduce computations. It utilizes the binomial distribution based on the characteristic of binary plane which is composed of only two elements: 0 and 1. Experimental results show that the proposed algorithm keeps its peak signal-to-noise ratio (PSNR) performance very close to the FSA-C1BT while the computation complexity is reduced considerably.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.509-517
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• 2001

Full-search algorithm requires large amount of computation which causes time delay or very complex hardware architecture for real time implementation. In this paper, we propose a fast motion estimator based on bit-plane matching, which reduce the computational complexity and the hardware cost. In the proposed motion estimator, the conventional motion estimation algorithms are applied to the binary images directly extracted from the video sequence. Furthermore, in the proposed VLSI motion estimator, we employ a Pair of processing cores that calculate the motion vector continuously By controlling the data flow in a systolic fashion using the internal shift registers in the processing cores, we avoid using SRAM (local memory) so that we remove the time overhead for accessing the local memory and adopt lower-cost fabrication technology. We modeled and tested the proposed motion estimator in VHDL, and then synthesized the whole system which has been integrated in a 0.6-$\mu$m triple-metal CMOS chip of size 8.15 X 10.84$\textrm{mm}^2$.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.258-268
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• 2001

The compression method is necessarily used to send the high quality moving picture that contains a number of data in image processing. In the field of moving picture compression method, the motion estimation algorithm is used to reduce the temporal redundancy. Block matching algorithm to be usually used is distinguished partial search algorithm with full search algorithm. Full search algorithm be used in this paper is the method to compare the reference block with entire block in the search window. It is very efficient and has simple data flow and control circuit. But the bigger the search window, the larger hardware size, because large computational operation is needed. In this paper, we design the full search block matching motion estimator. Using the DCT DC values, we decide luminance. And we apply 3 bit compare-selector using bit plane to I(Intra coded) picture, not using 8 bit luminance signals. Also it is suggested that use the same selective bit for the P(Predicted coded) and B(Bidirectional coded) picture. We compare based full search method with PSNR(Peak Signal to Noise Ratio) for C language modeling. Its condition is the reference block 8$\times$8, the search window 24$\times$24 and 352$\times$288 gray scale standard video images. The result has small difference that we cannot see. And we design the suggested motion estimator that hardware size is proved to reduce 38.3％ for structure I and 30.7％ for structure II. The memory is proved to reduce 31.3％ for structure I and II.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.3
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• pp.321-326
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• 2019

Image denoising methods based on block matching are founded on the experimental observations that neighboring patches or blocks in images retain similar features with each other, and have been proved to show superior performance in denoising different kinds of noise. The methods, however, take into account only neighboring blocks in searching for similar blocks, and ignore the characteristic features of the reference block itself. Consequently, denoising performance is negatively affected when outliers of the Gaussian distribution are included in the reference block which is to be denoised. In this paper, we propose an expanded block matching method in which noisy images are first decomposed into a number of bit-planes, then the range of true signals are estimated based on the distribution of pixels on the bit-planes, and finally outliers are replaced by the neighboring pixels belonging to the estimated range. In this way, the advantages of the conventional Gaussian filter can be added to the blocking matching method. We tested the proposed method through extensive experiments with well known test-bed images, and observed that performance gain can be achieved by the proposed method.