• Proceedings of the KIPE Conference
• /
• 2019.07a
• /
• pp.392-393
• /
• 2019

본 논문에서는 전기 보트 추진을 위한 SPMSM(Surface mounted Permanent Magnet Synchronous Motor) 구동 시스템을 개발하였다. 전차원 폐루프 관측기를 이용하여 외란 토크 관측기를 구성하고, 관측된 외란 성분을 속도 제어기 출력에 보상하여 속도 제어 성능을 향상시켰다. 리튬이온 배터리, 인버터 및 1kW SPMSM으로 구성된 전기 보트 추진 시스템을 이용한 구동 실험을 통해 추진용 전동기의 속도 제어 특성을 확인하였다.

• Proceedings of the KIPE Conference
• /
• 2019.07a
• /
• pp.384-385
• /
• 2019

본 논문에서는 단상 컨버터/3상 인버터 시스템에서 공통모드 전압 저감을 위한 PWM 기법을 제안한다. 컨버터/인버터 시스템은 스위칭에 의한 공통모드 전압으로 인해 전동기의 누설전류와 절연파괴 등의 문제가 발생할 수 있다. 이에 본 논문에서는 영전압벡터 인가시간에 따라 유효전압벡터의 위치를 선정하여 공통모드 전압을 저감하는 방법에 대해 제안한다. 모의실험을 통하여 제안된 기법의 효용성을 검증하였다.

• Journal of Sensor Science and Technology
• /
• v.7 no.2
• /
• pp.124-130
• /
• 1998

High-speed 3D vision systems are essential for autonomous robot or vehicle control applications. In our study, a stereo vision process has been developed. It consists of three steps : extraction of edges in right and left images, matching corresponding edges and calculation of the 3D map. This process is implemented in a VME 150/40 Imaging Technology vision system. It is a modular system composed by a display, an acquisition, a four Mbytes image frame memory, and three computational cards. Programmable accelerator computational modules are running at 40 MHz and are based on TMS320C31 DSP with a $64{\times}32$ bit instruction cache and two $1024{\times}32$ bit internal RAMs. Each is equipped with 512 Kbytes static RAM, 4 Mbytes image memory, 1 Mbytes flash EEPROM and a serial port. Data transfers and communications between modules are provided by three 8 bit global video bus, and three local configurable pipeline 8 bit video bus. The VME bus is dedicated to system management. Tasks between DSPs are distributed as follows: two DSPs are used to edges detection, one for the right image and the other for the left one. The last processor computes the matching process and the 3D calculation. With $512{\times}512$ pixels images, this sensor generates dense 3D maps at a rate of about 1 Hz depending of the scene complexity. Results can surely be improved by using a special suited multiprocessors cards.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37 no.4A
• /
• pp.189-196
• /
• 2012

A WAVE(Wireless Access for Vehicular Environment) system is a vehicle communication technology. The system provides the services to prevent vehicle accidents that might occur during driving. Also, it is used to provide various services such as monitoring vehicle management and system failure. However, the scrambler bit operation of WAVE system becomes less efficient in the organizations of software and hardware design because the parallel processing is impossible. Although scrambler algorithm proposed in this paper has different processing speed depending on input data 8 bit, 16 bit, 32 bit, and 64 bit. it improves the processing speed of the operation because it can make parallel processing possible depending on the input unit.

• Journal of Korean Society for Quality Management
• /
• v.21 no.2
• /
• pp.1-16
• /
• 1993

Early generations of products had little to no inherent capability to test themselves. The technologies involved often required only visual inspection and limited probing to troubleshoot the system once it was turned over to maintenance personnel. However, as the complexity of military and commercial systems grew, symptoms of failure became less noticeable to the operator. Therefore, the procedure to access, inspect, repair and replace a component became complicated, the requirements for personnel skill and testing equipment increased. and it took too long of a time to maintain a system. Meanwhile, the need for availability became more mission-critical and maintenance become very expensive. The obvious solution was to design in-system circuits or devices to self-test the primary system, the Built-In-Test(BIT) was born. This approach has continued right on up through present systems and is an integral part of systems now being designed. The object of this paper is to present a state-of-the-art research for filtering out the BIT diagnosis mistakes using Bayesian analysis and develop the algorithm for Redundant systems with BIT to improve BIT diagnosis.

• Journal of Information Technology Services
• /
• v.12 no.1
• /
• pp.1-14
• /
• 2013

The government has implemented operating the bus information terminal (hereinafter, 'BIT') to use by building it at a major bus station to solve the problem of traffic congestion. Busan Metropolitan City has been continuously expanding the installation of 'BIT' since 2003. However, there are few research on the factor to use and satisfaction survey on 'BIT' from the perspective of the users. This study, in an effort to inquire into the 'BIT' utilization factor and its vitalization plan, conducted a face to face survey of 172 citizens who had the experience in the 'BIT'. The result of the data analysis showed that usability, convenience, and availability were the critical factors for a BIT use. In addition, the general intention to use 'BIT' was found to be very high as much as 90.7%. The contributions of this study are as follows. The academic contributions is that it proved the relationship between usability, convenience and the intention to use suggested by the information technology acceptance model is supported even in case of 'BIT.' For the practitioners this study provides ground data for a local government to make a plan of a BIT extension.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.105-108
• /
• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Proceedings of the KIEE Conference
• /
• 1999.07g
• /
• pp.3067-3069
• /
• 1999

In this paper, A bit processor for controlling sequence logic was implemented, using a FPGA. This processor consists of program memory interface. I/O interface, parts for instruction fetch and decode, registers, ALU, program counter and etc. This FPGA is able to execute sequence instruction during program fetch cycle, because of divided bus system, program bus and data bus. Also this bit processor has instructions set that 16bit or 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package. Finally, the benchmark was performed to prove that Our FPGA has better performance than DSP(TMS320C32-40MHz) for the sequence logic control of PLC.

• Journal of Korea Multimedia Society
• /
• v.24 no.8
• /
• pp.1012-1019
• /
• 2021

Currently, since the black-white QR (Quick Response) codes have limited storage capacity, color QR codes have been actively being studied. By multiplexing 3 colors, the color QR codes can allow the code capacity to be increased by three times, however, the color multiplexing brings about the possibility of crosstalk and noises in the acquisition process of the final image, incurring the decrease of bit-recognition rate. In order to improve the bit recognition rate, while keeping the storage capacity high, this paper proposes a new type of color QR code which uses the pattern information as well as the color information, and then analyzes how to increase the bit recognition rate. For this aim, the paper presents an efficient system which extracts embedded information from color QR code and then, through practical experiments, it is shown that the proposed color QR codes improves the bit recognition rate and are useful for commercial applications, compared to the conventional color codes.

• Journal of Korea Society of Industrial Information Systems
• /
• v.20 no.6
• /
• pp.21-27
• /
• 2015

We analyze the problem that is occurring when using parity mode transformation required for 9 bit serial communication under Linux environment and propose the solution. The parity mode change is used for 9 bit serial communication in the Linux that by nature supports only 8 bit serial communication. delay (around OS tick) arises. Our analysis shows that the cause is minimum length of waiting time to transmit data remained in Tx FIFO buffers. A modified Linux serial driver proposed in this paper decreases the delay less than 1ms by using accurate time delaying. Despite various system communication interfaces, enormous existing standards and system have adopted RS-232 serial communication, and the part of them have communicated by 9bit serial.