• Title/Summary/Keyword: bit system

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A Low Density Parity Check Coding using the Weighted Bit-flipping Method (가중치가 부과된 Bit-flipping 기법을 이용한 LDPC 코딩)

  • Joh, Kyung-Hyun;Ra, Keuk-Hwan
    • 전자공학회논문지 IE
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    • v.43 no.4
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    • pp.115-121
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    • 2006
  • In this paper, we proposed about data error check and correction on channel transmission in the communication system. LDPC codes are used for minimizing channel errors by modeling AWGN Channel as a VDSL system. Because LDPC Codes use low density parity bit, mathematical complexity is low and relating processing time becomes shorten. Also the performance of LDPC code is better than that of turbo code in long code word on iterative decoding algorithm. This algorithm is better than conventional algorithms to correct errors, the proposed algorithm assigns weights for errors concerning parity bits. The proposed weighted Bit-flipping algorithm is better than the conventional Bit-flipping algorithm and we are recognized improve gain rate of 1 dB.

Performance Analysis of FH/CPFSK System in the Partial-band Jamming Noise (부분대역 재밍하에서 FH/CPFSK 시스템의 성능 분석)

  • 정근열;박진수
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.6 no.4
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    • pp.499-504
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    • 2002
  • In this paper, we analyzed the performance of FH/CPFSK system with differential detection in thermal noise, partial-band jamming noise and adjacent interference of all eight bit pattern. The parameters to analize performances of FH/CPFSK system have been used the bit rate, modulation index and performances of FH/CPFSK system with the differential detector have been presented with the optimum correlation function. And, we were compared with performance of FH/CPFSK and FH/BFSK system. In result, we could know that bit error probability of the approximation equation and exact equation nearly accorded in the high signal-to-noise ratio. And, we have been proved that FH/CPFSK system with differential detection according to jamming fraction ${\gamma}$ was worst to 3dB than FH/CPFSK system with limiter-discriminator. but was superior to 2dB than FH/BFSK.

Implementation of the Temperature Control System Using K-type Thermocouple (K형 열전대를 이용한 온도제어 시스템 구현)

  • Kim Jeong-Lae
    • Journal of the Korea Society of Computer and Information
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    • v.9 no.3
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    • pp.127-133
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    • 2004
  • This study was carried out develope a temperature control system of temperature control by used K-thermocouple. This system was producted a stable voltage regulator 22Bit of digital converter and 22Bit of resolution. It was producted a micro voltage of 25 times amplification and controlled a DC0.1V~DC4.7V within 0~120$0^{\circ}C$. We designed block-diagram of hardware and software by PIC16C74 in a micro-controller, we are made up of a VFD function and can be used interface of a power block.

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Multi-Rate and Multi-BEP Transmission Scheme Using Adaptive Overlapping Pulse-Position Modulator and Power Controller in Optical CDMA Systems

  • Miyazawa Takaya;Sasase Iwao
    • Journal of Communications and Networks
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    • v.7 no.4
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    • pp.462-470
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    • 2005
  • We propose a multi-rate and multi-BEP transmission scheme using adaptive overlapping pulse-position modulator (OPPM) and optical power controller in optical code division multiple access (CDMA) networks. The proposed system achieves the multi-rate and multi-BEP transmission by accommodating users with different values of OPPM parameter and transmitted power in the same network. The proposed scheme has advantages that the system is not required to change the code length and number of weight depending on the required bit rate of a user and the difference of bit rates does not have so much effect on the bit error probabilities (BEPs). Moreover, the difference of transmitted powers does not cause the change of bit rate. We analyze the BEPs of the four multimedia service classes corresponding to the com­binations of high/low-rates and low/high-BEPs and show that the proposed scheme can easily achieve distinct differentiation of the service classes with the simple system configuration.

EXCUTE REAL-TIME PROCESSING IN RTOS ON 8BIT MCU WITH TEMP AND HUMIDITY SENSOR

  • Kim, Ki-Su;Lee, Jong-Chan
    • Journal of the Korea Society of Computer and Information
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    • v.24 no.11
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    • pp.21-27
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    • 2019
  • Recently, embedded systems have been introduced in various fields such as smart factories, industrial drones, and medical robots. Since sensor data collection and IoT functions for machine learning and big data processing are essential in embedded systems, it is essential to port the operating system that is suitable for the function requirements. However, in embedded systems, it is necessary to separate the hard real-time system, which must process within a fixed time according to service characteristics, and the flexible real-time system, which is more flexible in processing time. It is difficult to port the operating system to a low-performance embedded device such as 8BIT MCU to perform simultaneous real-time. When porting a real-time OS (RTOS) to a low-specification MCU and performing a number of tasks, the performance of the real-time and general processing greatly deteriorates, causing a problem of re-designing the hardware and software if a hard real-time system is required for an operating system ported to a low-performance MCU such as an 8BIT MCU. Research on the technology that can process real-time processing system requirements on RTOS (ported in low-performance MCU) is needed.

64 Bit EISC Processor Design (64 Bit EISC 프로세서 설계)

  • 임종윤;이근택
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.161-164
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    • 2000
  • The architecture of microprocessor for a embedded system should be one that can perform more tasks with fewer instruction codes. The machine codes that high-level language compiler produces are mainly composed of specific ones, and codes that have small size are more frequently used. Extended Instruction Set Architecture (EISC) was proposed for that reason. We have designed pipe-line system for 64 bit EISC microprocessor. function level simulator was made for verification of design and instruction set architecture was also verified by that simulator. The behavioral function of synthesized logic was verified by comparison with the results of cycle-based simulator.

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Design of an 8-bit Color Adjustor for SDTV Using Verilog HDL (Verilog HDL을 이용한 SDTV용 8bit 색상 보정기의 설계)

  • Jeon, Byoung-Woong;Song, In-Chae
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.801-804
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    • 2005
  • In this paper, we designed an 8-bit color adjustor for SDTV using Verilog HDL. The conversion block requires a lot of multiplication. So we adopted Booth algorithm to reduce amount of operation and processing time. To improve speed, we designed the system output as parallel structure. We synthesized the designed system using Xilinx ISE and verified the operation through simulation using Modelsim.

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BASK System Design For Giga-Bit MODEM (Giga-Bit MODEM을 위한 BASK 시스템 설계)

  • Eom, Ki-Hwan;Kang, Seong-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.12
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    • pp.111-116
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    • 2005
  • We propose a BASK (Binary Amplitude Shift Keying) system for Giga-bit Modem in millimeter band. The proposed system consists of a high speed shutter of the transmitter and a repeater of the receiver. The shutter of the proposed system is introduced for pulse shaping to improve the intersymbol interference (ISI). The repeater consists of several stage converters. A converter is constructed with a low pass filter and a limiter. The repeater can improve the signal-to-noise ratio (SNR) and make the rectangular pulse train. The proposed system is a simple system that uses conversion method without IF (Intermediate Frequency) process.