• Title/Summary/Keyword: bit input

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Asymptotic Behavior of the output SINR at MMSE receivers in a MIMO MC-CDMA system (MIMO MC-CDMA시스템에서 MMSE 수신기 출력의 점근적 양상)

  • Kim, Kyeong-Yeon;Shim, Sei-Joon;Ham, Jae-Sang;Lee, Chung-Yong
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.44 no.4
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    • pp.10-16
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    • 2007
  • This paper analyzes the output signal-to-interference-plus-noise ratio (SINR) for a multiple-input-multiple-output (MIMO) multicarrier code division multiple access (MC-CDMA) system with minium mean square error receivers. A previous work of a single antenna MC-CDMA system cannot directly applied to a MIMO MC-CDMA system because some assumptions for single antenna do not match the case of multiple antenna. Therefore this paper expands the concept of freeness to MIMO system by using the Marcenko Pastur law. The analysis shows that the output SINR asymptotically converges to a deterministic value and finds the value on the assumption of freeness. From the analysis, it is easy to calculate bit error rate and the calculation is verified by simulations.

Sphere Decoding Algorithm and VLSI Implementation Using Two-Level Search (2 레벨 탐색을 이용한 스피어 디코딩 알고리즘과 VLSI 구현)

  • Huynh, Tronganh;Cho, Jong-Min;Kim, Jin-Sang;Cho, Won-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.6
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    • pp.104-110
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    • 2008
  • In this paper, a novel 2-level-search sphere decoding algorithm for multiple-input multiple-output (MIMO) detection and its VLSI implementation are presented. The proposed algorithm extends the search space by concurrently performing symbol detection on 2 level of the tree search. Therefore, the possibility of discarding good candidates can be avoided. Simulation results demonstrate the good performance of the proposed algorithm in terms of bit-error-rate (BER). From the proposed algorithm, an efficient very large scale integration (VLSI) architecture which incorporates low-complexity and fixed throughput features is proposed. The proposed architecture supports many modulation techniques such as BPSK, QPSK, 16-QAM and 64-QAM. The sorting block, which occupies a large portion of hardware utilization, is shared for different operating modes to reduce the area. The proposed hardware implementation results show the improvement in terms of area and BER performance compared with existing architectures.

VLSI Design of a 2048 Point FFT/IFFT by Sequential Data Processing for Digital Audio Broadcasting System (순차적 데이터 처리방식을 이용한 디지틀 오디오 방송용 2048 Point FFT/IFFT의 VLSI 설계)

  • Choe, Jun-Rim
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.5
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    • pp.65-73
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    • 2002
  • In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

On Adaptive LDPC Coded MIMO-OFDM with MQAM on Fading Channels (페이딩 채널에서 적응 LDPC 부호화 MIMO-OFDM의 성능 분석)

  • Kim, Jin-Woo;Joh, Kyung-Hyun;Ra, Keuk-Hwan
    • 전자공학회논문지 IE
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    • v.43 no.2
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    • pp.80-86
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    • 2006
  • The wireless communication based on LDPC and adaptive spatial-subcarrier coded modulation using MQAM for orthogonal frequency division multiplexing (OFDM) wireless transmission by using instantaneous channel state information and employing multiple antennas at both the transmitter and the receiver. Adaptive coded modulation is a promising idea for bandwidth-efficient transmission on time-varying, narrowband wireless channels. On power limited Additive White Gaussian Noise (AWGN) channels, low density parity check (LDPC) codes are a class of error control codes which have demonstrated impressive error correcting qualities, under some conditions performing even better than turbo codes. The paper demonstrates OFDM with LDPC and adaptive modulation applied to Multiple-Input Multiple-Output (MIMO) system. An optimization algorithm to obtain a bit and power allocation for each subcarrier assuming instantaneous channel knowledge is used. The experimental results are shown the potential of our proposed system.

Sharing based Admission Control Scheme for Service Differentiation in Optical Burst Switching Networks (광 버스트 스위칭 네트워크에서 서비스 차별화를 제공하는 공유 기반의 허락 제어 방식)

  • Paik, Junghoon
    • Journal of Broadcast Engineering
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    • v.20 no.5
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    • pp.748-755
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    • 2015
  • In this paper, sharing based admission control scheme is suggested for both service differentiation and improvement of wavelength utilization efficiency in burst switching networks. To provide service differentiation and high wavelength utilization efficiency, some of the wavelengths on a output link are shared with all classes and the others are used for the highest class exclusively. Markov based analysis is applied to the suggested scheme for the performance analysis and the numerical results are derived. The results are: The performance of lower traffic is more improved by the more number of shared wavelengths in case that the higher traffic or lower traffic is arrived equally or that the input rate of lower traffic is low. Another result is that the sharing effect of wavelengths is a little bit lowered when lower traffic passes the threshold.

Wavelet Lifting based ECG Signal Compression Using Multi-Stage Vector Quantization (다단계 벡터 양자화를 이용한 웨이브렛 리프팅 기반 ECG 압축)

  • Park, Seo-Young;Jeong, Gyu-Hyeok;Kim, Young-Ju;Lee, In-Sung;Joo, Gi-Ho
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.43 no.6 s.312
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    • pp.76-82
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    • 2006
  • In this paper, the biomedical signal compression method, which is combined with the multi-stage vector quantization and wavelet lifting scheme, is proposed. It utilizes the property of wavelet coefficients that give emphasis on approximation coefficients. The transmitted codebook index consists of the code vectors obtained by wavelet lifting coefficients of ECG and error signals from the 1024 block length, respectively. Each codebook is adaptively updated by the method comparing to the distance of input codevectors with candidate codevectors by using an pre-defined threshold value. The proposed compression method showed blow 3% in term of PRD and 276.62 bits/sec in term of CDR.

Design and Implementation of Efficient Symbol Detector for MIMO Spatial Multiplexing Systems (MIMO 공간 다중화 시스템을 위한 효율적인 심볼 검출기의 설계 및 구현)

  • Jung, Yun-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.10
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    • pp.75-82
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    • 2008
  • In this paper, we propose an efficient symbol detection algorithm for multiple-input multiple-output spatial multiplexing (MIMO-SM) systems and present its design and implementation results. By enhancing the performance of the first detected symbol which causes error propagation, the proposed algorithm achieves a considerable performance gain as compared to the conventional sorted QR decomposition (SQRD) based detection and the ordered successive detection (OSD) algorithms. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In case of 16QAM MIMO-SM system with 4 transmit and 4 receive ($4{\times}4$) antennas, at $BER=10^{-3}$ the proposed algorithm obtains the gai improvement of about 2.5-13.5 dB over the conventional algorithms. The proposed detection algorithm was designed in a hardware description language (HDL) and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. The results show that the proposed algorithm can be implemented without increasing the hardware costs significantly.

Dual Mode Buck Converter Capable of Changing Modes (모드 전환 제어 가능한 듀얼 모드 벅 변환기)

  • Jo, Yong-min;Lee, Tae-Heon;Kim, Jong-Goo;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.10
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    • pp.40-47
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    • 2016
  • In this paper, a dual mode buck converter with an ability to change mode is proposed, which is suitable particularly for portable device. The problem of conventional mode control circuit is affected by load variation condition such as suddenly or slowly. To resolve this problem, the mode control was designed with slow clock method. Also, when change from the PFM(Pulse Frequency Modulation) mode to the PWM(Pulse Width Modulation) mode, to use the counter to detect a high load. And the user can select mode transition point in load range from 20mA to 90mA by 3 bit digital signal. The circuits are implemented by using BCDMOS 0.18um 2-polt 3-metal process. Measurement environment are input voltage 3.7V, output voltage 1.2V and load current range from 10uA to 500mA. And measurement result show that the peak efficiency is 86% and ripple voltage is less 32mV.

MBus: A Fully Synthesizable Low-power Portable Interconnect Bus for Millimeter-scale Sensor Systems

  • Lee, Inhee;Kuo, Ye-Sheng;Pannuto, Pat;Kim, Gyouho;Foo, Zhiyoong;Kempke, Ben;Jeong, Seokhyeon;Kim, Yejoong;Dutta, Prabal;Blaauw, David;Lee, Yoonmyung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.6
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    • pp.745-753
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    • 2016
  • This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

Shore-to-sea Maritime Visible Light Communication using Color Clustered MIMO (컬러 클러스터 MIMO 기술을 적용한 해상 가시광 통신 시스템)

  • Kim, Hyeong-ji;Chung, Yeon-ho
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.19 no.8
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    • pp.1773-1779
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    • 2015
  • Shore-to-sea visible light communication using color clustered multiple-input and multiple-output (MIMO) is presented. The proposed maritime visible light communication (MVLC) offers a low-cost, high-speed wireless link for shore-to-sea maritime communications. Each color cluster is comprised of 50 red, green and blue (RGB) light emitting diodes (LEDs) and is modulated using on-off-keying (OOK). Selection combining is performed at the receiver, producing diversity effect within that color cluster. In this paper, we employ sea states (wave height, wind speed, etc.) data from both Pierson-Moskowitz and JONSWAP spectrum models under atmospheric turbulence conditions. Based on the simulation model, the maritime link quality is analysed in terms of coverage distance and bit error rate performance. The results show that the proposed system provides an efficient MVLC, while satisfying International Association of Lighthouse Authorities (IALA) requirements for maritime buoyage system and also offering sufficient illumination from high power LEDs.