• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.1-7
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• 2009

This paper describes design of high energy efficiency 32 bit parallel processor core using instruction-levels data gating and dynamic voltage scaling (DVS) techniques. We present instruction-levels data gating technique. We can control activation and switching activity of the function units in the proposed data technique. We present instruction-levels DVS technique without using DC-DC converter and voltage scheduler controlled by the operation system. We can control powers of the function units in the proposed DVS technique. The proposed instruction-levels DVS technique has the simple architecture than complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system and a hardware implementation is very easy. But, the energy efficiency of the proposed instruction-levels DVS technique having dual-power supply is similar to the complicated DVS which is DC-DC converter and voltage scheduler controlled by the operation system. We simulate the circuit simulation for running test program using Spectra. We selected reduced power supply to 0.667 times of the supplied power supply. The energy efficiency of the proposed 32 bit parallel processor core using instruction-levels data gating and DVS techniques can improve about 88.4% than that of the 32 bit parallel processor core without using those. The designed high energy efficiency 32 bit parallel processor core can utilize as the coprocessor processing massive data at high speed.

• Journal of the Korea Society for Simulation
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• v.18 no.2
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• pp.9-17
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• 2009

A face database has contained a large amount of facial information data since face recognition was widely used. With the increase of facial information data, the face recognition based on distributed processing method has been noticed as a major topic. In existing studies, there were lack of discussion about the transferring method for large data. So, we proposed a fuzzy logic-based bit compression rate selection method for distributed face recognition. The proposed method selects an effective bit compression rate by fuzzy inference based on face recognition rate, processing time for recognition, and transferred bit length. And, we compared the facial recognition rate and the recognition time of the proposed method to those of facial information data with no compression and fixed bit compression rates. Experimental results demonstrates that the proposed method can reduce processing time for face recognition with a reasonable recognition rate.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1313-1316
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• 1993

This paper presents a fuzzy system that estimates the optimal bit allocation matrices for the spatially active subimage classes of adaptive transform image coding in noisy channels. Transform image coding is good for image data compression but it requires a transmission error protection scheme to maintain the performance since the channel noise degrades its performance. The fuzzy system provides a simple way of estimating the bit allocation matrices from the optimal bit map computed by the method of minimizing the mean square error between the transform coefficients of the original and the reconstructed images.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.1
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• pp.55-61
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• 2003

The Data Encryption Standard(DES) has been a worldwide standard for over 20 years. DES is one of the block encryption techniques which ciphers 64-bit input data blocks using a 56-bit private key. The DES algorithm transforms 64-bit input in a series of steps into a 64-bit output. Thus, it is impossible to deduce the plaintext from the ciphertext which encrypted by this algorithm without the key. This paper presents an implementation of RFID roader system using the DES algorithm. An implemented system enhances the credibility of the encryption algorithm by using the Cipher Block Chining(CBC). Experimental results also show that the implemented system has better performance over the conventional commercial product.

• Journal of the Korea Society of Computer and Information
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• v.20 no.12
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• pp.1-8
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• 2015

Wear leveling techniques have been studied to prolong the lifetime of NAND flash memory. Most of studies have used Program/Erase(P/E) cycles as wear index for wear leveling. Unfortunately, P/E cycles could not predict the real lifetime of NAND flash blocks. Therefore, these algorithms have the limited performance from prolonging the lifetime when applied to the SSD. In order to apply the real lifetime, wear leveling algorithms, which use raw Bit Error Rate(rBER) as wear index, have been studied in recent years. In this paper, we propose CrEWL(Cold data identification using raw Bit error rate in Wear Leveling), which uses rBER as wear index to apply to the real lifetime. The proposed wear leveling reduces an overhead of garbage collections by using HBSQ(Hot Block Sequence Queue) which identifies hot data. In order to reduce overhead of wear leveling, CrEWL does not perform wear leveling until rBER of the some blocks reaches a threshold value. We evaluate CrEWL in comparison with the previous studies under the traces having the different Hot/Cold rate, and the experimental results show that our wear leveling technique can reduce the overhead up to 41% and prolong the lifetime up to 72% compared with previous wear leveling techniques.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.12
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• pp.1044-1052
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• 1990

We have investigated the digital bit synchronization problem in baseband communication receiver systems using the Gauss-Markov estimation technique which is equivalent to the weighted least square method. The realized bit synchronizer, including the data detector, processes the input signal two dimensionally into the transition phase and data level under the white Gaussian noise environment. We have confrmed the realiation of the bit synchronizer via computer simulation. In addition, we have compared and evaluated the estimation error performance of the proposed method with that of the conventional DTTL method and of the minimum likelihood method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.490-492
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• 2018

This paper presents an analysis of the AMR speech data as a basic work to study the technique of inputting and transmitting AMR voice data which is widely used in the public cell phone. AMR consists of HEADER and Speech Data, and it is transmitted in bit format and has 8 bit-rate modes in total. HEADER contains mode information of Speech Data, and the length of Speech Data differs depending on the mode. We chose the best mode which is best to input into QR code and analyzed that mode. It is a goal to show a higher compression ratio for voice data by the analysis and experiments. This analysis shows improvement in that it can transmit voice data more effectively.

• Journal of Biomedical Engineering Research
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• v.7 no.1
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• pp.53-58
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• 1986

This paper represent the design of a digital modem which transmits the ECG data from an ambulatory arrhythmia monitor over the telephone lines to a large hospital for the instantaneous interpretations. The digital modem provides on-line communications between the patient and the central computer located near cardiologists. For commercial telephone lines, the transmitting error rates of the digital modem were measured 200 times at a speed of 300 baud. In those measurements, the block errors-results, due to the misinterpretation of start and stop bits, did not occur, The data bit errors which were due to a single bit interpreted incorrectly were 0.78 (bits/10 ) . Since the acceptable data bit error limit is 10 per 106 bits transmitted, the digital modem designed in this paper can be used for the clinical applications without any difficulty.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.1
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• pp.121-125
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• 2006

A new GPS receiver correlator for the deeply-coupled GPS/INS integration system is proposed in order to the computation time problem of the Kalman filter. The proposed correlator consists of two early, prompt and late arm pairs. One pair is for detecting data bit transition boundary and another is for the correlator value calculation between input and replica signal. By detecting the data bit transition boundary, the measurement calculation time can be made longer than data bit period. As a result of this, the computational time problem of the integrated Kalman filter can be resolved. The validity of the proposed method is given through computer simulations.