• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.1
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• pp.88-94
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• 2005

This paper presents the design and implementation of a receiver operating between a rotary machine encoder and DSP. The receiver connects with the encoder using 1 bit serial data and DSP using 16 bits bus line. The receiver and encoder use the different operating frequency each other. We suggest a new apparatus and method of synchronized code for header detection in 1bit serial communication. The system operating frequency can be changed into 20MHz or 60MHz by using the external port such as 'clk_select'.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.229-232
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• 2000

AAL2 has been adopted for bandwidth-efficient trans-mission of low bit tate traffic over ATM networks in ITUT and ATM Forum. Since ATM/AAL2 is expected to be used as a switching technology in third-generation mobile access networks and mobile data traffic is expected to increase rapidly in near future, there must be a need for efficient scheduling scheme satisfying the QoS requirement of ow bit rate voice as well as the one of high bit rate data. In this paper, we propose a new class-scheduling scheme to improve data packet loss probability, while Qos of voice traffic is guaranteed, when data traffic is multiplexed together with mobile voice traffic into a single ATM VCC. The proposed scheme can efficiently support data traffic by assigning a time threshold value to voice traffic. Through simulation study, we show that the proposed scheme does not only achieve better efficiency for providing both mobile voice and data services than HOL class-scheduling scheme and normal FIFO scheme, but also guarantees mean voice packet delay under a certain criteria.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.30-39
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• 1994

A 1-chip high quality binarizing VLSI image processor (which has 8 bit ADC. 6 bit flash ADC, 15K standard cell, and 1K word ROM) based on 10 MIPS 16 bit DSP is implemented for FAX. This image processor(IP) performs image pre-processing. image quality improvement in copying and sending mode, and mixed image processing based on the fuzzy theory. And smoothing in sub-scan direction is applied for normal receiving mode data so the received data is enhanced like fine mode data. Each algorithm is processed with the same type of image processing window and 2-D image processing is implemented with a 1-D line buffer. The fabricated chip is applied to a FAX machine and image quality improvement is verified.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.5A
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• pp.517-525
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• 2006

In this paper, we present a high-speed RFID data filtering engine designed to carry out filtering under the conditions of massive data and massive filters. We discovered that the high-speed RFID data filtering technique is very similar to the high-speed packet classification technique which is used in high-speed routers and firewall systems. Actually, our filtering engine is designed based on existing packet classification algorithms, Bit Parallelism and Aggregated Bit Vector(ABV). In addition, we also discovered that there are strong temporal relations and redundancy in the RFID data filtering operations. We incorporated two kinds of caches, tag and filter caches, to make use of this characteristic to improve the efficiency of the filtering engine. The performance of the proposed engine has been examined by implementing a prototype system and testing it. Compared to the basic sequential filter comparison approach, our engine shows much better performance, and it gets better as the number of filters increases.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.11
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• pp.1-11
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• 1997

The transient current components of the dRAM are analyzed and the sensing current, data path operation current and DC leakage current are revealed to be the major curretn components. It is expected that the supply voltage of less than 1.5V with low VT MOS witll be used in multi-giga bit dRAM. A low voltage dual VT self-timed CMOS logic in which the subthreshold leakage current path is blocked by a large high-VT MOS is proposed. An active signal at each node of the nature speeds up the signal propagation and enables the synchronous DRAM to adopt a fast pipelining scheme. The sensing current can be reduced by adopting 8 bit prefetch scheme with 1.2V VDD. Although the total cycle time for the sequential 8 bit read is the same as that of the 3.3V conventional DRAM, the sensing current is loered to 0.7mA or less than 2.3% of the current of 3.3V conventional DRAM. 4 stage pipeline scheme is used to rduce the power consumption in the 4 giga bit DRAM data path of which length and RC delay amount to 3 cm and 23.3ns, respectively. A simple wave pipeline scheme is used in the data path where 4 sequential data pulses of 5 ns width are concurrently transferred. With the reduction of the supply voltage from 3.3V to 1.2V, the operation current is lowered from 22mA to 2.5mA while the operation speed is enhanced more than 4 times with 6 ns cycle time.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Korea Society of Computer and Information
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• v.29 no.7
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• pp.11-20
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• 2024

In this paper, we propose the BAG (Bit-width Aware Generator) and the Intermediate Layer Knowledge Distillation using Channel-wise Attention to reduce the knowledge gap between a quantized network, a full-precision network, and a generator in GDFQ (Generative Data-Free Quantization). Since the generator in GDFQ is only trained by the feedback from the full-precision network, the gap resulting in decreased capability due to low bit-width of the quantized network has no effect on training the generator. To alleviate this problem, BAG is quantized with same bit-width of the quantized network, and it can generate synthetic images, which are effectively used for training the quantized network. Typically, the knowledge gap between the quantized network and the full-precision network is also important. To resolve this, we compute channel-wise attention of outputs of convolutional layers, and minimize the loss function as the distance of them. As the result, the quantized network can learn which channels to focus on more from mimicking the full-precision network. To prove the efficiency of proposed methods, we quantize the network trained on CIFAR-100 with 3 bit-width weights and activations, and train it and the generator with our method. As the result, we achieve 56.14% Top-1 Accuracy and increase 3.4% higher accuracy compared to our baseline AdaDFQ.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.18 no.6
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• pp.1619-1637
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• 2024

In today's highly digitized landscape, securing digital communication is paramount due to threats like hacking, unauthorized data access, and network policy violations. The response to these challenges has been the development of cryptography applications, though many existing techniques face issues of complexity, efficiency, and limitations. Notably, sophisticated intruders can easily discern encrypted data during transmission, casting doubt on overall security. In contrast to encryption, steganography offers the unique advantage of concealing data without easy detection, although it, too, grapples with challenges. The primary hurdles in image steganography revolve around the quality and payload capacity of the cover image, which are persistently compromised. This article introduces a pioneering approach that integrates image steganography and encryption, presenting the BitPatternStego method. This novel technique addresses prevalent issues in image steganography, such as stego-image quality and payload, by concealing secret data within image pixels with identical bit patterns as their characters. Consequently, concerns regarding the quality and payload capacity of steganographic images become obsolete. Moreover, the BitPatternStego method boasts the capability to generate millions of keys for the same secret message, offering a robust and versatile solution to the evolving landscape of digital security challenges.

• The Journal of Internal Korean Medicine
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• v.25 no.4
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• pp.274-288
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• 2004

Objectives : This study was designed to evaluate the effect on cytotoxicity of Bojungikki-tang(BIT) in human lung cancer H460 cells. Methods : BIT-induced cell death was confirmed as apoptosis characterized by chromatin condensation and increase of the $sub-G_1$, DNA content. It was tested whether the water extract of BIT affects the cell cycle regulators such as, p2l/Cipl, p27/Kipl, cyclin $B_1$. Results : The data showed that treatment of BIT decreased the viability of H460 cells in a dose-dependent manner. p2l/Cip1 is gradually decreased by the addition of the cells with BIT extract. Interestingly, p27/Kip1 is not detected for 24 hr after the addition of BIT extract, however, after 24 hr, p27/Kipl markedly increased. In addition, cyclin $B_1$, decreased in a time dependent manner after the addition of the water extract. The activation of caspase -3 protease was further confirmed by degradation of procaspase-8 protease andpoly(ADP-ribose) polymerase(P ARP) by BIT in H460 cells. Moreover, BIT induced the increase of Bak expression. Conclusion : These results suggest that the extract of BIT exerts anticancer effects to induce the death of human lung cancer H460 cells via down regulation of cell cycle regulators such as p2l/Cip1, and cyclin B1 or up regulation of cell cycle regulators such as p27/Kip1. Moerover results suggest that BIT induces an apoptosis in H460 cells via activation of intrinsic caspase cascades.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.