• Journal of Intelligence and Information Systems
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• v.12 no.1
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• pp.107-123
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• 2006

We propose the Generalized Binary Second-order Recurrent Neural Networks(GBSRNNf) being equivalent to regular grammars and ?how the implementation of lexical analyzer recognizing the regular languages by using it. All the equivalent representations of regular grammars can be implemented in circuits by using GSBRNN, since it has binary-valued components and shows the structural relationship of a regular grammar. For a regular grammar with the number of symbols m, the number of terminals p, the number of nonterminals q, and the length of input string k, the size of the corresponding GBSRNN is $O(m(p+q)^2)$ and its parallel processing time is O(k) and its sequential processing time, $O(k(p+q)^2)$.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.365-368
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• 2001

This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

• Journal of the Korean Society for Precision Engineering
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• v.16 no.3 s.96
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• pp.174-179
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• 1999

A binary parallel robot manipulator uses actuators which have only two stable states and is structure is variable geometry truss. As a result, it has a finite number of states and fault tolerant mechanism because of kinematic redundancy. This kind of robot manipulator has the following advantages compared to a traditional one. Feedback control is not required, task repeatability can be very high, and finite state actuators are generally inexpensive. Because the number of states of a binary robot manipulator grows exponentially with the number of actuators, it is very difficult to solve an inverse kinematic problem. The goal of this paper is to develop an efficient algorithm to solve an inverse kinematic problem when the number of actuators are too much or the target position is located outside of workspace. The backbone curve is generated optimally by considering the curvature of the robot manipulator configuration and length of link. Then, the robot manipulator is fitted along the backbone curve with some criteria.

• Journal of applied mathematics & informatics
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• v.37 no.3_4
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• pp.163-176
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• 2019

Given a distribution of pebbles on the vertices of a connected graph G, a pebbling move is defined as the removal of two pebbles from some vertex and the placement of one of those pebbles at an adjacent vertex. The t-pebbling number, $f_t(G)$, of a connected graph G, is the smallest positive integer such that from every placement of $f_t(G)$ pebbles, t pebbles can be moved to any specified vertex by a sequence of pebbling moves. A graph G has the 2t-pebbling property if for any distribution with more than $2f_t(G)$ - q pebbles, where q is the number of vertices with at least one pebble, it is possible, using the sequence of pebbling moves, to put 2t pebbles on any vertex. In this paper, we determine the t-pebbling number for the middle graph of a complete binary tree $M(B_h)$ and we show that the middle graph of a complete binary tree $M(B_h)$ satisfies the 2t-pebbling property.

• Geomechanics and Engineering
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• v.12 no.4
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• pp.639-655
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• 2017

The binary mixture consists of two types of granular media with different physical attributes and sizes, which can be characterized by the percentage of large granules by weight (P) and the particle size ratio (${\alpha}$). Researchers determine that two thresholds ($P_S$ and $P_L$) exist for the peak shear strength of binary mixtures, i.e., at $P{\leq}P_S$, the peak shear strength is controlled by the small granules; at $P{\leq}P_L$, the peak shear strength is controlled by the large granules; at $P_S{\leq}P{\leq}P_L$, the peak shear strength is governed by both the large and small granules. However, the thresholds of binary mixtures with different ${\alpha}$ values, and the explanation related to the inner details of binary mixtures to account for why these thresholds exist, require further confirmation. This paper considers the mechanical behavior of binary mixtures with DEM analysis. The thresholds of binary mixtures are found to be strongly related to their coordination numbers $Z_L$ for all values of ${\alpha}$, where $Z_L$ denotes the partial coordination number only between the large particles. The arrangement structure of the large particles is examined when P approaches the thresholds, and a similar arrangement structure of large particles is formed in both 2D and 3D particle systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.3
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• pp.517-524
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• 2001

This paper describes a design of radix-2 SRT divider unit, which supports IEEE-754 floating-point standard, using redundant binary number system (RBNS). With the RBNS, the partial quotient decision logic can operate about 20-% faster, as well as can be implemented with a simple hardware when compared to the conventional methods based on two's complement arithmetic. By using a new redundant binary adder proposed in this paper, the mantissa divider is efficiently implemented, thus resulting in about 20% smaller area than other works. The divider unit supports double precision format, five exceptions and four rounding modes. It was verified with Verilog HDL and Verilog-XL.

• Journal of Korea Society of Industrial Information Systems
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• v.7 no.5
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• pp.67-72
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• 2002

The number of keystream cycle sequences has been proposed as a characteristic of binary sequence generators for cryptographic applications, but in general most binary sequence generators have the only one-cycle sequence. In this paper, we propose a switching-tap LFSR as a basic function of a multiple-cycle binary sequence generator and the improved Rueppel's multiple-cycle generator. Finally we analyze its period, linear complexity, and the number of its keystream cycle sequences.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2001.05a
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• pp.105-108
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• 2001

In this paper, the learning algorithm called advanced expanded and truncate algorithm(AETLA) is proposed to training multilayer binary neural network to approximate binary to binary mapping. AETLA used merit of ETL and MTGA learning algorithm. We proposed to new learning algorithm to decrease number of hidden layer. Therefore, learning speed of the proposed AETLA learning algorithm is much faster than other learning algorithm.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.195-198
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• 2000

It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.2
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• pp.29-37
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• 1997

A new algorithm and parallel architecture for high-speed complex number multiplication is presented, and a prototype chip based on the proposed approach is designed. By employing redundant binary (RB) arithmetic, an N-bit complex number multiplication is simplified to two RB multiplications (i.e., an addition of N RB partial products), which are responsible for real and imaginary parts, respectively. Also, and efficient RB encoding scheme proposed in this paper enables to generate RB partial products without additional hardware and delay overheads compared with binary partial product generation. The proposed approach leads to a highly parallel architecture with regularity and modularity. As a results, it results in much simpler realization and higher performance than the classical method based on real multipliers and adders. As a test vehicle, a prototype 8-b complex number multiplier core has been fabricated using $0.8\mu\textrm{m}$ CMOS technology. It contains 11,500 transistors on the area of about $1.05 \times 1.34 textrm{mm}^2$. The functional and speed test results show that it can safely operate with 200 MHz clock at $V_{DD}=2.5 V$, and consumes about 90mW.