• 제목/요약/키워드: binary number

검색결과 769건 처리시간 0.024초

정규문법과 동등한 일반화된 이진 이차 재귀 신경망 (Generalized Binary Second-order Recurrent Neural Networks Equivalent to Regular Grammars)

  • 정순호
    • 지능정보연구
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    • 제12권1호
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    • pp.107-123
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    • 2006
  • 이 논문은 정규문법과 동등한 의미를 가지는 일반적인 이진 이차 재귀 신경망(Generalized Binary Second-order Recurrent Neural Networks: GBSRNN)의 구조 및 학습 방법을 제안하며 이를 이용하여 정규언어를 인식하는 어휘분석기 구현을 소개한다. GSBRNN는 성분들의 이진값 표현으로 정규문법과 동치인 모든 표현에 대하여 하드웨어로 표현할 수 있는 방법을 제공하며 정규 문법과의 구조적 관련성을 보여준다. 정규문법에서 심볼들의 개수 m, 비단말 심볼의 개수 p, 단말 심볼의 개수 q, k인 문자열이 입력된다고 할 때, GBSRNN의 크기는 $O(m(p+q)^2)$ 이고 병렬처리 시간은 O(k)이며 순차처리 시간은 $O(k(p+q)^2)$이다.

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고속 여분 부동 소수점 이진수의 제산/스퀘어-루트 설계 및 제작 (A Design and Fabrication of the High-Speed Division/square-Root using a Redundant Floating Point Binary Number)

  • 김종섭;이종화;조상복
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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    • pp.365-368
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    • 2001
  • This paper described a design and implementation of the division/square-root for a redundant floating point binary number using high-speed quotient selector. This division/square-root used the method of a redundant binary addition with 25MHz clock speed. The addition of two numbers can be performed in a constant time independent of the word length since carry propagation can be eliminated. We have developed a 16-bit VLSI circuit for division and square-root operations used extensively in each iterative step. It peformed the division and square-root by a redundant binary addition to the shifted binary number every 16 cycles. Also the circuit uses the nonrestoring method to obtain a quotient. The quotient selection logic used a leading three digits of partial remainders in order to be implemented in a simple circuit. As a result, the performance of the proposed scheme is further enhanced in the speed of operation process by applying new quotient selection addition logic which can be parallelly process the quotient decision field. It showed the speed-up of 13% faster than previously presented schemes used the same algorithms.

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등뼈 곡선을 이용한 2진 로봇 머니퓰레이터의 역기구학적 해석 (A Study on the Inverse kinematic Analysis of a Binary Robot Manipulator using Backbone Curve)

  • 류길하;이인석
    • 한국정밀공학회지
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    • 제16권3호통권96호
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    • pp.174-179
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    • 1999
  • A binary parallel robot manipulator uses actuators which have only two stable states and is structure is variable geometry truss. As a result, it has a finite number of states and fault tolerant mechanism because of kinematic redundancy. This kind of robot manipulator has the following advantages compared to a traditional one. Feedback control is not required, task repeatability can be very high, and finite state actuators are generally inexpensive. Because the number of states of a binary robot manipulator grows exponentially with the number of actuators, it is very difficult to solve an inverse kinematic problem. The goal of this paper is to develop an efficient algorithm to solve an inverse kinematic problem when the number of actuators are too much or the target position is located outside of workspace. The backbone curve is generated optimally by considering the curvature of the robot manipulator configuration and length of link. Then, the robot manipulator is fitted along the backbone curve with some criteria.

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PEBBLING ON THE MIDDLE GRAPH OF A COMPLETE BINARY TREE

  • LOURDUSAMY, A.;NELLAINAYAKI, S. SARATHA;STEFFI, J. JENIFER
    • Journal of applied mathematics & informatics
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    • 제37권3_4호
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    • pp.163-176
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    • 2019
  • Given a distribution of pebbles on the vertices of a connected graph G, a pebbling move is defined as the removal of two pebbles from some vertex and the placement of one of those pebbles at an adjacent vertex. The t-pebbling number, $f_t(G)$, of a connected graph G, is the smallest positive integer such that from every placement of $f_t(G)$ pebbles, t pebbles can be moved to any specified vertex by a sequence of pebbling moves. A graph G has the 2t-pebbling property if for any distribution with more than $2f_t(G)$ - q pebbles, where q is the number of vertices with at least one pebble, it is possible, using the sequence of pebbling moves, to put 2t pebbles on any vertex. In this paper, we determine the t-pebbling number for the middle graph of a complete binary tree $M(B_h)$ and we show that the middle graph of a complete binary tree $M(B_h)$ satisfies the 2t-pebbling property.

Analysis of the thresholds of granular mixtures using the discrete element method

  • Jian, Gong;Jun, Liu
    • Geomechanics and Engineering
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    • 제12권4호
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    • pp.639-655
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    • 2017
  • The binary mixture consists of two types of granular media with different physical attributes and sizes, which can be characterized by the percentage of large granules by weight (P) and the particle size ratio (${\alpha}$). Researchers determine that two thresholds ($P_S$ and $P_L$) exist for the peak shear strength of binary mixtures, i.e., at $P{\leq}P_S$, the peak shear strength is controlled by the small granules; at $P{\leq}P_L$, the peak shear strength is controlled by the large granules; at $P_S{\leq}P{\leq}P_L$, the peak shear strength is governed by both the large and small granules. However, the thresholds of binary mixtures with different ${\alpha}$ values, and the explanation related to the inner details of binary mixtures to account for why these thresholds exist, require further confirmation. This paper considers the mechanical behavior of binary mixtures with DEM analysis. The thresholds of binary mixtures are found to be strongly related to their coordination numbers $Z_L$ for all values of ${\alpha}$, where $Z_L$ denotes the partial coordination number only between the large particles. The arrangement structure of the large particles is examined when P approaches the thresholds, and a similar arrangement structure of large particles is formed in both 2D and 3D particle systems.

Redundant Binary 수치계를 이용한 radix-2 SRT부동 소수점 제산기 유닛 설계 (A Design of Radix-2 SRT Floating-Point Divider Unit using ]Redundant Binary Number System)

  • 이종남;신경욱
    • 한국정보통신학회논문지
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    • 제5권3호
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    • pp.517-524
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    • 2001
  • IEEE-754 부동소수점 표준을 지원하는 radix-2 SRT 제산기 유닛을 redundant binary (RB) 수치계를 이용하여 설계하였다. RB 수치계를 이용함으로써 기존의 2의 보수 수치계를 이용하는 경우에 비해 부분 몫 결정 회로의 동작속도를 약 20-% 향상시킴과 아울러 회로 단순화를 이루었다. 또한, 새로운 RB 가산기 회로를 제안함으로써 가수 제산기를 효율적으로 구현하여 기존의 방식에 비해 면적을 약 20-%의 감소시켰다. 설계된 부동소수점 제산기는 배정도 형식과 5가지의 예외처리 및 4가지의 반올림 모드를 지원하며, Verilog HDL로 설계되어 Verilog-XL로 검증하였다.

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A Proposal on a Multiple-Cycle Binary Sequence Generator with a ST-LFSR

  • Lee, Hoon-Jae;Park, Hee-Bong
    • 한국산업정보학회논문지
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    • 제7권5호
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    • pp.67-72
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    • 2002
  • 출력 키수열의 사이클 수가 암호 분야에서 새로운 평가 요소로서 제안된 바 있으나 대부분의 이진 수열 발생기는 출력 사이클이 1개 뿐인 것으로 알려져 있다 본 논문에서는 다수 사이클을 갖는 발생기의 기본 함수로서 switching-tap LFSR과 이를 응용한 Rueppel 개선형 다수열 발생기를 제안하였다. 그리고 개선된 발생기에 대하여 주기, 선형 복잡도 및 출력 사이클 수에 대하여 안전성을 분석하였다.

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AETLA를 이용한 이진 신경회로망의 최적 합성방법 (Optimal Method for Binary Neural Network using AETLA)

  • 성상규;정종원;이준탁
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 2001년도 춘계학술대회 학술발표 논문집
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    • pp.105-108
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    • 2001
  • In this paper, the learning algorithm called advanced expanded and truncate algorithm(AETLA) is proposed to training multilayer binary neural network to approximate binary to binary mapping. AETLA used merit of ETL and MTGA learning algorithm. We proposed to new learning algorithm to decrease number of hidden layer. Therefore, learning speed of the proposed AETLA learning algorithm is much faster than other learning algorithm.

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CMOS-Based Fuzzy Operation Circuit Using Binary-Coded Redundantly-Represented Positive-Digit Numbers

  • Tabata, Toru;Ueno, Fumio;Eguchi, Kei;Zhu, Hongbing
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 ITC-CSCC -1
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    • pp.195-198
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    • 2000
  • It is possible to perform the digital fuzzy logical high-speed and high-precision computation by the use of redundantly-represented binary positive-digit number arithmetic operation. In this paper, as basic operation circuits in the fuzzy logic new voltage-mode 4-valued binary parallel processing operation circuits using positive redundantly-expressed binary-coded numbers is discussed.

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Redundant binary 연산을 이용한 고속 복소수 승산기 (A high-speed complex multiplier based on redundant binary arithmetic)

  • 신경욱
    • 전자공학회논문지C
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    • 제34C권2호
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    • pp.29-37
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    • 1997
  • A new algorithm and parallel architecture for high-speed complex number multiplication is presented, and a prototype chip based on the proposed approach is designed. By employing redundant binary (RB) arithmetic, an N-bit complex number multiplication is simplified to two RB multiplications (i.e., an addition of N RB partial products), which are responsible for real and imaginary parts, respectively. Also, and efficient RB encoding scheme proposed in this paper enables to generate RB partial products without additional hardware and delay overheads compared with binary partial product generation. The proposed approach leads to a highly parallel architecture with regularity and modularity. As a results, it results in much simpler realization and higher performance than the classical method based on real multipliers and adders. As a test vehicle, a prototype 8-b complex number multiplier core has been fabricated using $0.8\mu\textrm{m}$ CMOS technology. It contains 11,500 transistors on the area of about $1.05 \times 1.34 textrm{mm}^2$. The functional and speed test results show that it can safely operate with 200 MHz clock at $V_{DD}=2.5 V$, and consumes about 90mW.

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