• Journal of Sensor Science and Technology
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• v.30 no.5
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• pp.295-299
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• 2021

In this study, we present a complementary metal-oxide-semiconductor (CMOS) binary image sensor. It can shoot an object rotating at a high-speed by using a gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector. The GBT PMOSFET-type photodetector amplifies the photocurrent generated by light. Therefore, it is more sensitive than a standard N+/P-substrate photodetector. A binary operation is installed in a GBT PMOSFET-type photodetector with high-sensitivity characteristics, and the high-speed operation is verified by the output image. The binary operations circuit comprise a comparator and memory of 1- bit. Thus, the binary CMOS image sensor does not require an additional analog-to-digital converter. The binary CMOS image sensor is manufactured using a standard CMOS process, and its high- speed operation is verified experimentally.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.305-308
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• 2001

This paper describes the design of elliptic curve cryptographic (ECC) coprocessor over binary fields for the If card. This coprocessor is implemented by the shift-and-add algorithm for the field multiplication algorithm. And the modified almost inverse algorithm(MAIA) is selected for the inverse multiplication algorithm. These two algorithms is merged to minimize the hardware size. Scalar multiplication is performed by the binary Non Adjacent Format(NAF) method. The ECC we have implemented is defined over the field GF(2$^{163}$), which is a SEC-2 recommendation［7］..

• Journal of the Korean Society of Visualization
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• v.15 no.2
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• pp.21-25
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• 2017

If a liquid droplet evaporates on a solid substrate, when it completely dries, it leaves a peculiar pattern, which depends on the composition of the liquid. Not only a single component liquid but also complex liquids are studied for a different purpose. In particular, a binary mixture droplet has been widely studied and used for an ink-jet printing technology. In this study, we focus on investigating to visualize the internal flow field of an ethanol-water mixture by varying a concentration ratio between two liquids. We measure the in-plane velocity vector fields and vorticities. We believe that this fundamental study about the internal flow field provides a basic idea to understand the dried pattern of the binary mixture droplet.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.3A
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• pp.221-230
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• 2002

This paper presents a new moving object segmentation algorithm using markov random field. The algorithm is based on signal detection theory. That is to say, motion of moving object is decided by binary decision rule, and false decision is corrected by markov random field model. The procedure toward complete segmentation consists of two steps: motion detection and object segmentation. First, motion detection decides the presence of motion on velocity vector by binary decision rule. And velocity vector is generated by optical flow. Second, object segmentation cancels noise by Bayes rule. Experimental results demonstrate the efficiency of the presented method.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.8
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• pp.1044-1051
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• 2020

The age of quantum computers is coming soon. In order to prepare for the upcoming future, the National Institute of Standards and Technology has recruited candidates to set standards for post quantum cryptography to establish a future cryptography standard. The submitted ciphers are expected to be safe from quantum algorithm attacks, but it is necessary to verify that the submitted algorithm is safe from quantum attacks using quantum algorithm even when it is actually operated on a quantum computer. Therefore, in this paper, we investigate an efficient quantum gate implementation for binary field multiplication of code based post quantum cryptography to work on quantum computers. We implemented the binary field multiplication for two field polynomials presented by Classic McEliece and three field polynomials presented by ROLLO in generic algorithm and Karatsuba algorithm.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.25-28
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• 2001

A theory of binary wavelets has been recently proposed by using two-band perfect reconstruction filter banks over binary field . Binary wavelet transform (BWT) of binary images can be used as an alternative to the real-valued wavelet transform of binary images in image processing applications such as compression, edge detection, and recognition. The BWT, however, requires large amount of computations since its operation is accomplished by matrix multiplication. In this paper, a fast BWT algorithm which utilizes filtering operation instead or matrix multiplication is presented . It is shown that the proposed algorithm can significantly reduce the computational complexity of the BWT. For the decomposition and reconstruction or an N ${\times}$ N image, the proposed algorithm requires only 2LN$^2$ multiplications and 2(L-1)N$^2$addtions when the filter length is L, while the BWT needs 2N$^3$multiplications and 2N(N-1)$^2$additions.

• Journal of Sensor Science and Technology
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• v.27 no.6
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• Journal of the Korean Society for Industrial and Applied Mathematics
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• v.13 no.3
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• pp.225-236
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• 2009

Image inpainting is the process of reconstructing lost or deteriorated parts of images using information from surrounding areas. We propose a computationally efficient and fast phase-field method which uses automatic switching parameter, adaptive time step, and automatic stopping of calculation. The algorithm is based on an energy functional. We demonstrate the performance of our new method and compare it with a previous method.

• Bulletin of the Korean Mathematical Society
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• v.29 no.1
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• pp.89-99
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• 1992

In this paper we will prove some theorems on the period and the linear complexity of certain sequences in GF(q) which are generated by combining two sequences in a reasonable way. In fact these theorems are generalizations of the main result in [1]. A sequence of elements of GF(2) is called a binary sequence. In recent years considerable interest has been shown in the generation of binary sequences which have good properties. Such binary sequences play an important role in a stream cipher system.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.246-248
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• 2022

Binary Edwards curves (BEdC), a new form of elliptic curves proposed by Bernstein, satisfy the complete addition law without exceptions. This paper describes an efficient hardware implementation of point scalar multiplication on BEdC using projective coordinates. Modified Montgomery ladder algorithm was adopted for point scalar multiplication, and binary field arithmetic operations were implemented using 257-bit binary adder, 257-bit binary squarer, and 32-bit binary multiplier. The hardware operation of the BEdC crypto-core was verified using Zynq UltraScale+ MPSoC device. It takes 521,535 clock cycles to compute point scalar multiplication.