• Journal of Electrical Engineering and Technology
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• v.4 no.2
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• pp.240-248
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• 2009

An approach to control the position for an interior permanent magnet synchronous motor (IPMSM) based on an adaptive integral binary observer is described. The binary controller with a binary observer is composed of a main loop regulator and an auxiliary loop regulator. One of its key features is that it alleviates chatter in the constant boundary layer. However, steady state estimation accuracy and robustness are dependent upon the thickness of the constant boundary layer. In order to improve the steady state performance of the binary observer and eliminate the chattering problem of the constant boundary layer, a new binary observer is formed by adding extra integral dynamics to the existing switching hyperplane equation. Also, the proposed adaptive integral binary observer applies an adaptive scheme because the parameters of the dynamic equations such as the machine inertia and the viscosity friction coefficient are not well known. Furthermore, these values can typically be easily changed during normal operation. However, the proposed observer can overcome the problems caused by using the dynamic equations, and the rotor position estimation is constructed by integrating the rotor speed estimated with a Lyapunov function. Experimental results obtained using the proposed algorithm are presented to demonstrate the effectiveness of the approach.

• Journal of IKEEE
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• v.22 no.3
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• pp.850-853
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• 2018

In this paper, we propose a decoding method using a balanced binary tree and a canonical Huffman tree for efficient decoding of Huffman codes. The balanced binary tree scheme reduces the number of searches by lowering the height of the tree and binary search. However, constructing a tree based on the value of the code instead of frequency of symbol is a drawback of the balanced binary tree. In order to overcome these drawbacks, a balanced binary tree is reconstructed according to the occurrence probability of symbols at each level of the tree and binary search is performed for each level. We minimize the number of searches using a canonical Huffman tree to find level of code to avoid searching sequentially from the top level to bottom level.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.246-248
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• 2022

Binary Edwards curves (BEdC), a new form of elliptic curves proposed by Bernstein, satisfy the complete addition law without exceptions. This paper describes an efficient hardware implementation of point scalar multiplication on BEdC using projective coordinates. Modified Montgomery ladder algorithm was adopted for point scalar multiplication, and binary field arithmetic operations were implemented using 257-bit binary adder, 257-bit binary squarer, and 32-bit binary multiplier. The hardware operation of the BEdC crypto-core was verified using Zynq UltraScale+ MPSoC device. It takes 521,535 clock cycles to compute point scalar multiplication.

• Journal of Korea Society of Digital Industry and Information Management
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• v.11 no.3
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• pp.11-19
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• 2015

Due to recent development in mobile devices, the mobile device utilization and many related applications have been increasing. Most of initial applications on mobile devices just showed simple information, but now they processes huge data. However, smart devices have certain limitations in processing massive data. Especially, if the size of data increases, the speed of data processing adversely decreases, so the performance of programs also decreases. If hardware specification of the mobile devices is not enough to handle it, response time will be drastically delayed. To overcome these drawbacks, most of application running on mobile devices communicate with their servers to manage data. XML is a proper language for data communication to send and receive data between servers and mobile devices, because it defines rules of document's format and it is a textual data format and small-sized language. However, mobile devices have limitation such as memory, CPU and wireless network to process huge data and XML also takes a lot of time to communicate with servers and devices and handle data, so it could be overhead in service time. Binary XML is an alternative of performance improvement in data processing, which has XML's benefits and minimizes the XML size by binary coding. However, most of binaryXML which are used on applications don't fit on mobile applications. In this paper, we surveyed many kinds of binaryXML, compared merits and demerits to find a binaryXML for mobile applications. We propose how to use binary XML and implemented an electronic attendance system using binary XML to overcome the limitation of XML and to reduce the load of data communications between servers and devices.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.6
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• pp.567-572
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• 2019

In this paper, we propose an algorithm to perform convolution, pooling, and ReLU operations in CNN using binary image and binary kernel. It decomposes 256 gray-scale images into 8 bit planes and uses a binary kernel consisting of -1 and 1. The convolution operation of binary image and binary kernel is performed by addition and subtraction. Logically, it is a binary operation algorithm using the XNOR and comparator. ReLU and pooling operations are performed by using XNOR and OR logic operations, respectively. Through the experiments to verify the usefulness of the proposed algorithm, We confirm that the CNN operation can be performed by converting it to binary logic operation. It is an algorithm that can implement deep running even in a system with weak computing power. It can be applied to a variety of embedded systems such as smart phones, intelligent CCTV, IoT system, and autonomous car.

• Asian-Australasian Journal of Animal Sciences
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• v.18 no.8
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• pp.1088-1097
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• 2005

Main objectives of this study were to investigate accuracy, bias and power of linear and threshold model segregation analysis methods for detection of major genes in categorical traits in farm animals. Maximum Likelihood Linear Model (MLLM), Bayesian Linear Model (BALM) and Bayesian Threshold Model (BATM) were applied to simulated data on normal, categorical and binary scales as well as to disease data in pigs. Simulated data on the underlying normally distributed liability (NDL) were used to create categorical and binary data. MLLM method was applied to data on all scales (Normal, categorical and binary) and BATM method was developed and applied only to binary data. The MLLM analyses underestimated parameters for binary as well as categorical traits compared to normal traits; with the bias being very severe for binary traits. The accuracy of major gene and polygene parameter estimates was also very low for binary data compared with those for categorical data; the later gave results similar to normal data. When disease incidence (on binary scale) is close to 50%, segregation analysis has more accuracy and lesser bias, compared to diseases with rare incidences. NDL data were always better than categorical data. Under the MLLM method, the test statistics for categorical and binary data were consistently unusually very high (while the opposite is expected due to loss of information in categorical data), indicating high false discovery rates of major genes if linear models are applied to categorical traits. With Bayesian segregation analysis, 95% highest probability density regions of major gene variances were checked if they included the value of zero (boundary parameter); by nature of this difference between likelihood and Bayesian approaches, the Bayesian methods are likely to be more reliable for categorical data. The BATM segregation analysis of binary data also showed a significant advantage over MLLM in terms of higher accuracy. Based on the results, threshold models are recommended when the trait distributions are discontinuous. Further, segregation analysis could be used in an initial scan of the data for evidence of major genes before embarking on molecular genome mapping.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.2B
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• pp.71-79
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• 2006

Address lookup is an essential function in the Internet routers, and it determines overall router performance. In this paper, we have thoroughly investigated the binary-search-based address lookup algorithms and proposed a new algorithm based on binary search on prefix lengths. Most of the existing binary search schemes perform binary search on prefix values, and hence the lookup speed is proportional to the length of prefixes or the log function of the number of prefixes. The previous algorithm based on binary search on prefix lengths has superior lookup performance than others. However, the algorithm requires very complicated pre-computation of markers and best matching prefixes in internal nodes since naive binary search is not possible in their scheme. This complicated pre-computation makes the composition of the routing table and incremental update very difficult. By using leaf-pushing, the proposed algorithm in this paper removes the complicated pre-computation of the Previous work in performing the binary search on prefix lengths. The performance evaluation results show that the proposed scheme has very good performance in lookup speed compared with previous works.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.3
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• pp.177-182
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• 2008

Because output of multi-code CDMA system adapted high speed data transmission becoming multi-level system use linear amplifier in output stage and complex output signal. Therefore, Multi-Code CDMA system has shortcoming of high price, high complexity etc. Binary CDMA technology that allow fetters in existing CDMA technology to supplement this shortcoming proposed. In binary CDMA system When correlator process high speed data, bottle-neck phenomenon is happened on synchronization acquisition process, it is very important parameter. Because existent correlator must there be advantage that power consumption is small but flow addition of several stages to receive correlation's value, the processing speed has disadvantage because the operation amount is much. Therefore in this paper, proposed correlator has characteristic such as data is able to high speed processing, chip area is independent and power consumption is constant in structure in binary CDMA system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.5B
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• pp.285-295
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• 2008

Internet routers perform packet forwarding which determines a next hop for each incoming packet using the packet's destination IP address. IP address lookup becomes one of the major challenges because it should be performed in wire-speed for every incoming packet under the circumstance of the advancement in link technologies and the growth of the number of the Internet users. Many binary search algorithms have been proposed for fast IP address lookup. However, tree-based binary search algorithms are usually unbalanced, and they do not provide very good search performance. Even for binary search algorithms providing balanced search, they have drawbacks requiring prefix duplication. In this paper, a new binary search algorithm which provides the balanced binary search and the number of its entries is much less than the number of original prefixes. This is possible because of composing the binary search tree only with disjoint prefixes of the prefix set. Each node has a prefix vector that has the prefix nesting information. The number of memory accesses of the proposed algorithm becomes much less than that of prior binary search algorithms, and hence its performance for IP address lookup is considerably improved.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.1
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• pp.122-128
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• 2003

In this paper, a 16${\times}$16-bit Multiplier and Accumulator (MAC) is designed using a Redundant Binary Adder (RBA) circuit so that it can make a fast addition of the Redundant Binary Partial Products (RB_PP's) by using Wallace-tree structure. Because a RBA adds two RB numbers, it acts as a 4-2 compressor, which reduces four inputs to two output signals. We propose a method to convert the Redundant Binary (RB) representation into the 2's complement binary representation. Instead of using the conventional full adders, a more efficient RB number to binary number converter can be designed with new conversion method.