• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.49-55
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• 2022

In the next generation mobile communication systems, hybrid massive multiple-input multiple output (MIMO) can be used to highly improve an achievable rate without increasing the number of RF chains. Recently, successive-interference-cancellation (SIC) based hybrid precoder design scheme was proposed to reduce the complexity. However, since this scheme uses simple diagonal matrix for baseband precoding, it cannot solve an interference problem between the transmitted streams. Also, there is a limitation for improving the data rate because of the use of one phase shifter for analog precoding. To solve these problems, in this paper we propose a digital precoding based on the SVD of the effective channel and an analog precoding using two phase shifters. Through simulation, we show that the proposed scheme has better achievable rate and SINR performances than the conventional one.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.12A
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• pp.1172-1176
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• 2008

In this paper, we describe the implementation and performance of a dual-mode Software Define Radio (SDR) smart antenna base station system. SDR technology enables a communication system to be reconfigured through software downloads to the flexible hardware platform that is implemented using programmable devices such as Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs), and microprocessors. The presented base station channel card comprises the physical layer (pHY) including the baseband modem as well as the beamforming module. This channel card is designed to support TDD High-Speed Downlink Packet Access (HSDPA) as well as Wireless Broadband Portable Internet (WiBro) utilizing the SDR technology. We first describe the operations and functions required in WiBro and TDD HSDPA. Then, we explain the channel card design procedure and hardware implementation. Finally, we evaluate WiBro and TDD HSDPA performance by simulation and actual channel-card-based processing. Our smart antenna base-station dual-mode channel card shows flexibility and tremendous performance gains in terms of communication capacity and cell coverage.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.18-27
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• 2004

In this paper, we presents an analytical simulation procedure for evaluation in baseband digital modulated signals distortions in the present of RF power amplifier(SSPA) nonlinear behavior and backoff operations of OFDM wireless transmission system. we obtained the optimum nonlinear transfer function of designed SSPA with the SiGe HBT bias currents of OFDM multi-channel wireless transmission system and compared this transfer function to SSPA nonlinear modeling functions mathematically, we finds optimum bias conditions of designed SSPA. With the derived nonlinear modeling function of SSPA, We analysed the PSD characteristics of in-band and out-band output powers of SSPA EVM measurement results of distorted constellation signals with the input power levels of SSPA. The results of paper can be applied to find the SSPA linearly with optimum bias currents and determine the SSPA input backoff bias for AGC control circuits of SSPA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.9C
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• pp.729-734
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• 2010

In the initial stage of the communications between a base station and a satellite transponder, the base station transmits the frequency-sweeping un-modulated up-link carrier within a certain frequency range to acquire the doppler frequency shift and signal power between the base station and the satellite in orbital flight. The satellite transponder acquires and tracks the carrier in order to initialize the communication. To control such initialization process, the satellite receiver should analyze the input carrier signal in various ways. This paper presents an SNR estimation algorithm to control the initialization process. The proposed algorithm converts the input signal into the baseband polar coordinate representation and estimates the SNR via the statistics of the angular signal components as well as the status parameters to control the receiver. The Monte-Carlo simulations shows the validity of the estimation proposed.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.9
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• pp.11-20
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• 1998

High-speed complex-number arithmetic units are essential to baseband signal processing of modern digital communication systems such as channel equalization, timing recovery, modulation and demodulation. In this paper, a new complex-number multiplication algorithm is proposed, which is based on redundant binary (RB) arithmetic combined with radix-4 Booth recoding scheme. The proposed algorithm reduces the number of partial product by one-half as compared with the conventional direct method using real-number multipliers and adders. It also leads to a highly parallel architecture and simplified circuit, resulting in high-speed operation and low power dissipation. To demonstrate the proposed algorithm, a prototype complex-number multiplier-accumulator (CMAC) core with 10-bit operands has been designed using 0.8-$\mu\textrm{m}$ N-Well CMOS technology. The designed CMAC core contains about 18,000 transistors on the area of about 1.60 ${\times}$ 1.93 $\textrm{mm}^2$. The functional and speed test results show that it can operate with 120-MHz clock at V$\sub$DD/=3.3-V, and its power consumption is given to about 63-mW.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.3
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• pp.132-139
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• 2016

In the bandpass sampling(BPS), the sampling frequency for the analog-to-digital converter is lower than that of the signal to be sampled. Since the BPS operation results in the signal spectrum to be copied on the baseband, it is possible for the frequency down-converter to be conveniently omitted. The second-order BPS system is introduced in order to cancel the aliased interference components from the BPS output that may be generated by the BPS processing. In this paper, we introduce a design method for the optimal phase of the interpolant filter in the second-order BPS system which enables to maximally cancel the aliased components. Being mathematically derived, this method can always be applied independently to the spectral characteristics of the BPS input signal. The performance improvements by the suggested method has been measured statistically with various power spectra of the received signal, and it has been shown that the maximal amount of the improvements reaches up to 5~20 [dB] in comparison with the previous suboptimal algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.274-279
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• 2021

Since conventional massive antenna systems require too many RF chains, they have disadvantages of high implementation cost and complexity. To overcome this problem, hybrid precoding schemes have been proposed. But, they are still of high implementation cost and complexity because RF chains are connected to all antenna elements. In this paper, we consider massive MIMO systems with overlapped sub-array (OSA) structure and then, propose a hybrid precoding scheme. In the overlapped subarray structure, RF analog precoding matrix has a sparse structure where many elements of RF analog precoding matrix are zeros. Using this sparse property, we propose a GTP-based precoder design method for RF and baseband digital precoding. Through simulation, we show that the proposed scheme has more than 85% of the spectral efficiency of the fully-connected structure while having 20~30% of complexity of it.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.80-87
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• 2006

SONY corporation preoccupies $80\%$ of a market of the CCD used in a CCTV system. The CCD of SONY have high duality which can not follow the progress of capability. But there are some problems which differ the clock frequency used in CCD from the frequency used in common video encoder. To get the result by using common video encoder, the system needs a scaler that could adjust image size and PLL that synchronizes CCD's with encoder's clock So, this paper proposes the video encoder that is activated at equal clock used in CCD without scaler and PLL. The encoder converts ITU-R BT.601 4:2:2 or ITU-R BT.656 inputs from various video sources into NTSC or PAL signals in CVBS. Due to variable clock, property of filters used in the encoder is automatically changed by clock and filters adopt multiplier-free structures to reduce hardware complexity. The hardware bit width of programmable digital filters for luminance and chrominance signals, along with other operating blocks, are carefully determined to produce hish-quality digital video signals of ${\pm}1$ LSB error or less. The proposed encoder is experimentally demonstrated by using the Altera Stratix EP1S80B953C6ES device.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.5
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• pp.547-555
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• 2008

This parer proposed the path mismatch detection and compensation algorithm with closed form for linear amplification with non-linear components(LINC) system implementation. The LINC system has a merit of using the high efficient amplifier by transferring the non-constant envelop signal which is high peak to average signal ratio into constant envelop signal. However, the performance degradation is very sensitive to the path mismatch such as an amplitude mismatch and a phase mismatch. In order to improve the path mismatch, the error detection and compensation method is introduced by the use of four test signals. Since the presented method has the closed form solution, the efficient and fast detection is available. The digital-IF structure of LINC system applied by the proposed error detection and compensation algorithm was implemented. The performance was evaluated with the IEEE 802.16 WiMAX baseband sinal which has 7 MHz channel bandwidth and 16-QAM. The Error Vector Magnitude(EVM) of -37.37 dB was obtained through performance test, which meets performance requirement of -24 dB EVM. As a result, the introduced error detection and compensation method was verified to improve the LINC system performance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.