• The Journal of Korea Robotics Society
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• v.4 no.1
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• pp.1-9
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• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2313-2315
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• 2003

This paper presents the development methods which Samsung GPS baseband chip is called S3E4510X. Specification of S3E4510X and design methodology of baseband architecture is presented with a study of their effects. Also GPS core block and software are described in detail. We designed and implemented the test board with RF module for evaluating performance via static test dynamic test and each performance factors using live signal and CPS simulator. Test results show that our development GPS baseband chip have effectively performance for mobile handset Location Based Service (LBS) and its practical use for navigation.

• ETRI Journal
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• v.31 no.6
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• pp.795-802
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• 2009

This paper presents the design of an advanced terrestrial digital multimedia broadcasting (AT-DMB) baseband receiver SoC. The AT-DMB baseband is incorporated into a hierarchical modulation scheme consisting of high priority (HP) and low priority (LP) stream decoders. The advantages of the hierarchical modulation scheme are backward compatibility and an enhanced data rate. The structure of the HP stream is the same as that of the conventional T-DMB system; therefore, a conventional T-DMB service is possible by decoding multimedia data in an HP stream. An enhanced data rate can be achieved by using both HP and LP streams. In this paper, we also discuss a time deinterleaver that can deinterleave data for a time duration of 384 ms or 768 ms. The interleaving time duration is chosen using the LP symbol mapping scheme. Furthermore, instead of a Viterbi decoder, a turbo decoder is adopted as an inner error correction system to mitigate the performance degradation due to a smaller symbol distance in a hierarchically modulated LP symbol. The AT-DMB baseband receiver SoC is fabricated using 0.13 ${\mu}m$ technology and shows successful operation with a 50 mW power dissipation.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.255-258
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• 2003

To design the Bluetooth core efficiently, I analyzed the entire architecture and basic functions in the baseband and attempted to implement a Bluetooth one-chip solution on the basis of the Bluetooth SIG specification 1.1. We implemented important blocks into the hardware and firmware and found increased efficiency implementation when compared with the results of the implementation that using the criterion of size, Performance, stability, etc. And then to connect the baseband to the SE3208 core of the EISC type, we defined the baseband register and discovered a suitable method by comparing two results with the two connection ways.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.258-258
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• 2004

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.9-17
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• 2007

This paper shows an implementation of the baseband processor compliant with the IEEE 802.11a standard. Some innovative techniques are proposed to fulfill the mandatory requirements of the standard. For verification and analysis of this design, we use a Platform-based SoC (system on chip) environment. The entire system consists of test-board for the baseband processor chip and the SoC platform for implementing MAC (medium access control).

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.1733-1736
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• 2005

본 논문에서는 기존의 설계 방법의 문제점을 해결하기 위한 설계 방법인 플랫폼 기반 설계에서 사용할 수 있는 DSP 기반 플랫폼을 구현하였다. 구현된 DSP 기반 플랫폼을 AMBA AHB 버스를 바탕으로한 듀얼프로세서 플랫폼과 crossbar switch 구조의 버스 구조를 가지고 4개의 프로세서를 연결한 멀티프로세서 플랫폼으로 확장하여 검증함으로서 이질적인 환경에서 동작함을 나타내었다. 멀티프로세서 플랫폼에서는 DVB-T baseband 수신기를 HW/SW 분할 구현하고 성능 평가를 수행하였다. DSP 기반 플랫폼은 유연성, 확장성, 고속의 연산의 특징을 가진다.

• Journal of Korea Society of Digital Industry and Information Management
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• v.4 no.4
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• pp.9-19
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• 2008

In this paper, it is studied anti-collision algorithm based on the transmission protocol for RFID baseband system of the lSO/IEC 18000-6 Type-C regulation and designed the baseband part of RFID reader system using FPGA. To compensate this weak point of the slot random aloha algorithm which must have a long time to be dumped before deciding an appropriate slot size according to the number of surrounding tag, we suggested how to apply Bit By Bit algorithm to be able to recognize the tag when the tag is clashing. The design of the baseband part in the RFID reader system is accomplish by use of the ISE9.1i and I made an experiment on it targeting Spartan2. Construction verification is measured each block through Logic Analyzer and I can verify it has no error. I also compared and analyzed the performance between proposed algorithm and past algorithm and verified the improvement of performance.

• ETRI Journal
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• v.25 no.5
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• pp.328-336
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• 2003

Bluetooth is a specification for short-range wireless communication using the 2.4 GHz ISM band. It emphasizes low complexity, low power, and low cost. This paper describes an area-efficient digital baseband module for wireless technology. For area-efficiency, we carefully consider hardware and software partitioning. We implement complex control tasks of the Bluetooth baseband layer protocols in software running on an embedded microcontroller. Hardware-efficient functions, such as low-level bitstream link control; host controller interfaces (HCIs), such as universal asynchronous receiver transmitter (UART) and universal serial bus (USB)interfaces; and audio Codec are performed by dedicated hardware blocks. Furthermore, we eliminate FIFOs for data buffering between hardware functional units. The design is done using fully synthesizable Verilog HDL to enhance the portability between process technologies so that our module can be easily integrated as an intellectual property core no system-on-a-chip (SoC) ASICs. A field programmable gate array (FPGA) prototype of this module was tested for functional verification and realtime operation of file and bitstream transfers between PCs. The module was fabricated in a $0.25-{\mu}m$ CMOS technology, the core size of which was only 2.79 $mm{\times}2.80mm$.

• ETRI Journal
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• v.30 no.1
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• pp.141-151
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• 2008

In this paper, we introduce a new verification platform with ARM- and DSP-based multiprocessor architecture. Its simple communication interface with a crossbar switch architecture is suitable for a heterogeneous multiprocessor platform. The platform is used to verify the function and performance of a DVB-T baseband receiver using hardware and software partitioning techniques with a seamless hardware/software co-verification tool. We present a dual-processor platform with an ARM926 and a Teak DSP, but it cannot satisfy the standard specification of EN 300 744 of DVB-T ETSI. Therefore, we propose a new multiprocessor strategy with an ARM926 and three Teak DSPs synchronized at 166 MHz to satisfy the required specification of DVB-T.