• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.4
• /
• pp.86-93
• /
• 2008

A low-power, low-noise, highly-linear hybrid balun circuit is proposed for 2.4-GHz fully differential CMOS direct conversion receivers. The hybrid balun is composed of a passive transformer and loss-compensating auxiliary amplifiers. Design issues regarding the optimal signal splitting and coupling between the transformer and compensating amplifiers are discussed. Implemented in $0.18{\mu}m$ CMOS process, the 2.4 GHz hybrid balun achieves 2.8 dB higher gain and 1.9 dB lower noise figure than its passive counterpart and +23 dBm of IIP3 only at a current consumption of 0.67 mA from 1.2 V supply. It is also examined that the hybrid balun can remarkably lower the total noise figure of a 2.4 GHz fully differential RF receiver only at a cost of 0.82 mW additional power dissipation.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.10 no.5
• /
• pp.947-954
• /
• 2009

This paper proposed a new balanced power amplifier using the reflected input of conventional balanced power amplifiers composed of branch line hybrid coupler. In general, the single-ended amplifier in balanced amplifiers does not have the perfect matching, so the reflected input power, in other words the leakage power, is terminated conventionally at the isolation port of hybrid coupler. However in this work, the leakage power is injected into the auxiliary amplifier, and its output power is combined to the output power of balanced amplifier. Therefore output power, efficiency, and 2-tone IMD3 performances of the proposed balanced amplifier are highly improved compared to the conventional balanced amplifier. For the verification of the proposed balanced amplifier, a conventional balanced amplifier and the proposed balanced amplifier are designed, fabricated and measured, and the measured results are compared. The proposed balanced amplifier shows the improvement in the output power(Pout), power added efficiency (PAE), and 2-tone IMD3 by 3dB, 5.2%, and $5{\sim}10dBc$, respectively, from the measurement.

• Journal of IKEEE
• /
• v.23 no.2
• /
• pp.403-406
• /
• 2019

We propose a low-loss on-chip transformer using an auxiliary primary part (APP) for an output matching network for fully integrated CMOS power amplifiers. The APP is designed using a fifth metal layer while the primary and secondary parts are designed using a sixth metal layer with a width smaller than that of the primary and secondary parts of the transformer to minimize the substrate loss and the parasitic capacitance between the primary and secondary parts. By adapting the APP in the on-chip transformer, we obtain an improved maximum available gain value without the need for any additional chip area. The feasibility of the proposed APP structure is successfully verified.

• Proceedings of the IEEK Conference
• /
• 1998.06a
• /
• pp.859-862
• /
• 1998

An offset compensation scheme for rail-to-rail CMOS op-amps with complementary input stages is presented. Two auxiliary amplifiers are used to compensate for the offsets of NMOS and PMOS differnetial input stages, and ping-pong control is employed for continuous-time operation. Simulation and measurements resutls show that offsets are reduced about 20 times by this scheme.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.12
• /
• pp.40-48
• /
• 1998

An offset compensation scheme for rail-to-rail CMOS op-amps with complementary input stages is presented. Two auxiliary amplifiers are used to compensate for the offsets of NMOS and PMOS differential input stages, and ping-pong control is employed for continuous-time operation. A 3V offset-compensated rail-to-rail CMOS op-amp has been designed and fabricated using a 0.8$\mu\textrm{m}$ single-poly, double-metal CMOS process. Measurement results show that offsets are reduced about 20 times by this scheme.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.35D no.10
• /
• pp.13-21
• /
• 1998

In this paper, we analyze the main-carrier cancellation characteristics of the nulling loop control circuit which is used for the main-carrier cancellation circuit of the feedforward linear power amplifier. A new nulling loop error control method is proposed to improve the linear power amplifier characteristics. With this analysis, the main carrier cancellation ratio can be estimated and the required specifications of the main and auxiliary amplifiers can be optimized for the economic and power efficiency.