• 마이크로전자및패키징학회지
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• 제17권4호
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• International Journal of Advanced Culture Technology
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• 제8권1호
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• pp.207-212
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• 2020

The human centric lighting (HCL) control is a major focus point of the smart lighting system design to provide energy efficient and people mood rhythmic motivation lighting in smart buildings. This paper proposes the HCL control using indoor surveillance camera to improve the human motivation and well-beings in the indoor environments like residential and industrial buildings. In this proposed approach, the indoor surveillance camera video streams are used to predict the day lights and occupancy, occupancy specific emotional features predictions using the advanced computer vision techniques, and this human centric features are transmitted to the smart building light management system. The smart building light management system connected with internet of things (IoT) featured lighting devices and controls the light illumination of the objective human specific lighting devices. The proposed concept experimental model implemented using RGB LED lighting devices connected with IoT features open-source controller in the network along with networked video surveillance solution. The experiment results are verified with custom made automatic lighting control demon application integrated with OpenCV framework based computer vision methods to predict the human centric features and based on the estimated features the lighting illumination level and colors are controlled automatically. The experiment results received from the demon system are analyzed and used for the real-time development of a lighting system control strategy.

• 한국미생물·생명공학회지
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• 제21권4호
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• pp.354-365
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• 1993

A novel control method with automatic tuning of PID controller parameters has been developed for efficient regulation of dissolved oxygen concentration in fed-batch fermentations of Escherichia coli. Agitation speed and oxygen partial pressure in the inlet gas stream were chosen to be the manipulated variables. A heuristic reasoning allowed improved tuning decisions from the supervision of control performance indices and it coule obviate the needs for process assumptions or disturbance patterns. The control input consisted of feedback and feedforword parts. The feedback part was determined by PID control and the feedforward part is determined from the feed rate. The proportional gain was updated on-line by a set of heuristics rules based on the supervision of three performance indices. These indices were output error covariance, the average value of output error, and input covariance, which were calculated on-line using a moving window. The integral and derivative time constants were determined from the period of output response. The specific growth rate was maintained at a low level to avoid acetic acid accumulation and thus to achieve a high cell density. The specific growthe rate was estimated from the carbon dioxide evolution rate. In fed-batch fermentation, the simutaneous control of dissolved oxygen concentration (at 0.2; fraction of saturated value) and specific growth rate (at 0.25$hr^{-1}$) was satisfactory for the entire culture period in spite of the changes in the feed rate and the switching of control input.

• 생물환경조절학회지
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• 제6권4호
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• pp.242-249
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• 1997

현대화 온실이 농가에 보급 된지 5년째를 맞고 있지만 환경조절을 위한 자동화 설비의 이용현황은 외국으로부터 수입된 일부 유리온실을 제외하고는 당초 목적한 성능과 기술에 이르지 못하고 있어 그 이용율이 아주 저조하다. 이것은 농민의 자동화 장치 이용기술 부족 때문이기도 하지만 자동화 장치의 하드웨어 및 소프트웨어가 농민에 의한 수동스위치 조작보다 제어 성능이 따르지 못한 것이 주된 이유라고 생각된다. 이에 본 연구는 지금까지 외국기술에 의존하거나 이용율이 낮은 원예시설의 환경조절자동제어 시스템을 국내 기술에 의해 생산 보급할 수 있도록 성능이 우수하고 적응성이 높은 시스템 개발을 위하여 수행한 연구결과를 요약하면 다음과 같다. 1. 온실의 고온관리를 위한 온실내외의 온도차를 함수로하여 창개례순서, 1회 개폐폭, 제어주기 둥을 결정하는 알고리즘을 개발하여, 제어프로그램을 작성하였으며 시스템을 운전하여 본 결과 제어성능이 우수하였다. 2. 파이프비닐온실에는 시스템의 설치 및 A/S의 편리성 등을 감안하여 각 환경요인별로 개별제어 할 수 있도록 시스템화하는 것이 바람직하다고 판단되었다. 3. 시스템의 실용화를 위하여 제어항목 중 관수, 탄산가스 농도, 커덴개폐는 타이머를 이용한 시퀀스제어로 하였다. 4. DSP칩을 이용하여 고온제어를 위한 창개폐제어 시스템을 실용화할 수 있도록 개발하였다. 5. 온실의 자동제어시스템과 연결되어 있는 전화를 통하여 관리자가 부재 중 온실의 과고온, 정전, 고장 둥 비상발생시 관리자에게 무선호출을 할 수 있는 경보시스템을 개발하였다.

• 대한의용생체공학회:의공학회지
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• 제18권1호
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• pp.25-36
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• 1997

To regulate cardiac output of the Total Artificial Heart(TAH) physiologically, the hemodynamic information must be toed back to the controller. So far, our group has developed an automatic cardiac output control algorithm using the motor current waveform, It is, however difficult to detect the preload level such as a filling status of ventricular inflow and the variation of atrial pressures within normal physiologic range(0-15 mmHg) by analyzing the motor current which simultaneously reflects the afterload effect. On the other hin4 the interventricular volume pressure(IVP) which is not influenced by arterload but by preload is a good information source for the estimation of preload states. In order to find the relationship between preload and IVP waveform, we set up the artificial heart system on the Donovan type mock circulatory system and measured the IVP waveform, right and left atrial pressures, inflow and outflow waveforms and the signals represented the information of moving actuator's position. We shows the feasibility of estimating the hemodynamic changes of inflow by using IVP waveform. fife found that the negative peak value of IVP waveform is linearly related to atrial pressures. And we also found that we could use the time to reach the negative peak in IVP waveform, the time to open outflow valve, the area enclosed IVP waveform as unfu parameters to estimate blood filling volume of diastole ventricle. The suggested method has advantages of avoiding thrombogenesis, bacterial niche formation and increasing longterm reliability of sensor by avoiding direct contact to blood.

• 대한전자공학회논문지SD
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• 제46권9호
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• pp.58-67
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• 2009

본 논문에서는 높은 대역폭과 넓은 동적 영역을 갖는 DVB-S2를 위한 새로운 디지털 이득 제어 시스템을 제안하였다. DVB-S2 시스템의 PAPR은 매우 크며, 요구되는 정착 시간은 매우 작기 때문에 일반적인 폐-루프 아날로그 이득 제어 방식은 사용할 수 없다. 정확한 이득 제어와 기저 대역 모뎀과의 직접적인 인터페이스를 위해서 디지털 이득 제어가 필요하다. 또한 아날로그 이득 제어 방식에 비해 정착 시간과 공정, 전압, 온도 값의 변화에 둔감한 이점을 갖는다. 본 논문에서는 세밀한 해상도와 넓은 이득 영역을 갖기 위해서 AGC 시스템 및 구성회로를 제안하였다. 이 시스템은 높은 대역폭의 디지털 VGA와 넓은 파워 범위를 가진 RMS 검출기, 저 전력의 SAR 타입 ADC, 그리고 디지털 이득 제어기로 구성되어 있다. 파워 소모와 칩면적을 줄이기 위해 한 개의 SAR 타입 ADC를 사용했으며, ADC 입력은 4개의 파워 검출기를 사용하여 시간 축 상에서 인터리빙 방식으로 구현하였다. 모의실험 및 측정 결과는 제안하는 AGC 시스템의 이득 에러가 $10{\mu}s$ 내에서, 0.25 dB보다 낮은 것을 보여주고 있다. 전체 칩은 $0.18{\mu}m$ CMOS 공정을 사용하여 설계하였다. 제안된 IF AGC 시스템의 측정 결과는 0.25 dB의 해상도와 80 dB의 이득 범위, 8 nV/$\sqrt{Hz}$의 입력 기준 잡음, $IIP_3$는 5 dBm, 전력 소모는 60 mW임을 보여주고 있다. 파워검출기는 100 MHz 입력에서 35 dB의 동적 영역을 갖는다.