• Journal of KIISE:Information Networking
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• 제30권2호
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• pp.270-281
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• 2003

ETF made the RFCs of MPLS technologies for providing the QoS of ATM or Frame Relay and the flexibility&scalability of IP on the Internet services. IETF has been expanding MPLS technologies as a common control component for supporting the various switching technologies called GMPLS. Also, IETF has standardized the signaling protocols based on such technologies, such as LDP, CR-LDP and RSVP-TE. ETRI developed the MPLS system based on ATM switch in order to provide more reliable services, differentiated services and value-added services like the VPN and traffic engineering service on the Korea Public Sector network. We are planning on deploying model services and commercial services on that network. This paper explains the basic functions of LDP, design and development of LDP on our system, and compares with LDP development and operation on other MPLS systems made by Cisco, Juniper, Nortel and Riverstone. In conclusion, this paper deduces the future services and applications by LDP through these explanation and comparison.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2479-2484
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• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• 제36권2호
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• pp.185-194
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• 2008

In this paper, an efficient technique is proposed to integrate the 3D user interface with the tiled display system in PC cluster environment. In the developed 3D user interface software, various menus are provided to increase the user friendliness of the interface, including the several model-control-commands. To eliminate the noise produced from the 3D user interface devices, the box filtering algorithm is employed. Further, a communication splitting algorithm, which is a kind of asynchronous communication method, is proposed to reduce the motion delay between the 3D interface and the tiled display system, and its efficiency is validated through the benchmarking tests.

• The Transactions of the Korea Information Processing Society
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• 제4권6호
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• pp.1433-1442
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• 1997

Algorithm design is needed to optimized bandwidth which satisfy quality of service(QoS) requirements of vary traffic classes for Multimedia service in ATM networks. The diverse flow characteristics e.g., burstiness, bit rate and burst length, have to guarantee the different quality of service(QoS) requirements in Asynchronous Transfer Mode(ATM). The QoS parameter may be measured in terms of cell loss probability and maximum cell dely. In this paper, we consider the ATM networks which the virtual path(vip) concept is implemented by applying the Markov Modulated Deterministic Process method. We develop an efficient algorithm to computer the minimum capacity required to satisfy all the QoS requirements when multiple classes of on-off source are multiplexed on single VP. Using above the result, we propose a simple algorithm to determine the VP combination to achieve the near optimum of total capacity required for satisfying the individual QoS requirements. Numerical results are also presented to demonstrate the performance of the algorithm, when compared to the optimal total capacity required.

• Journal of Positioning, Navigation, and Timing
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• 제6권4호
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• pp.167-179
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• 2017

In this paper, a simplified Cubature Kalman Filter (SCKF) is proposed to reduce the computation load of CKF, which is then used as a filter for transfer alignment of shipboard INS. CKF is an approximate Bayesian filter that can be applied to non-linear systems. When an initial estimation error is large, convergence characteristic of the CKF is more stable than that of the Extended Kalman Filter (EKF), and the reliability of the filter operation is more ensured than that of the Unscented Kalman Filter (UKF). However, when a system degree is large, the computation amount of CKF is also increased significantly, becoming a burden on real-time implementation in embedded systems. A simplified CKF is proposed to address this problem. This filter is applied to shipboard inertial navigation system (INS) transfer alignment. In the filter design for transfer alignment, measurement type and measurement update rate should be determined first, and if an application target is a ship, lever-arm problem, flexure of the hull, and asynchronous time problem between Master Inertial Navigation System (MINS) and Slave Inertial Navigation System (SINS) should be taken into consideration. In this paper, a transfer alignment filter based on SCKF is designed by considering these problems, and its performance is validated based on simulations.

• Journal of The Korean Association of Information Education
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• 제12권2호
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• pp.141-149
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• 2008

Congruence of figure is a basic to learn a symmetrical figure and helps to understand the characteristics of figure and know the way of drawing figures. The knowledge of congruence provides us art attainments to understand design and fine pieces of art. However, it is difficult to expect the interaction between students or between teachers and students, because of spending too much time for cutting papers and making the shapes of figure during the class for establishing the concepts. This study utilized a question-based interaction model which would foster elementary school student's learning effectiveness and make them understood the concept of congruence, also developed a congruence learning system which could communicate in both synchronous and asynchronous situation.

• The Journal of Korean Institute of Communications and Information Sciences
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• 제27권5C호
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• Journal of the Institute of Electronics and Information Engineers
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• 제49권12호
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• pp.45-55
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• 2012

The energy efficiency is extremely significant in Wireless Sensor Networks (WSN) which deliver the data sensed in the sensor field, using wireless communications. Under the characteristics of WSN, many MAC protocols employ the Duty Cycle mechanism which continuously operates Wakeup and Sleep periods, for the energy efficiency. However, constant Wakeup period in general Duty Cycle incurs the limited performance of the energy efficiency and the receiving ratio. For addressing this, we design and propose a new scheme called Variable Wakeup Period, considering local traffic conditions. Our scheme enhances receiving ratio by increasing Wakeup period under the high traffic condition, and makes high energy efficiency by decreasing Wakeup period under the otherwise condition. In addition, we evaluate the performance of our scheme by performing the simulation, which experiments the previous synchronous and asynchronous MAC protocols, and which also experiments the same protocols with the proposed scheme, for comparative evaluations.

• Journal of the Korean Institute of Telematics and Electronics
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• 제26권5호
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• pp.108-116
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• 1989

The simulator described here-LOSIM(LOgic SIMulator)-was developed to verify the logic design for VLSI(Very Large Scale Integrated) circuits at mixed level. In this paper, we present a modeling approach to obtain more accurate results than conventional logic simulators [5-6,9] for general elements, functional elements, transmission gates and tri-state gates using eight signal values and two gignal strengths. LOSIM has the capability which can perform timing and hazard analysis by using assignable rise and fall delays. We also prosent an efficient algorithm to accurately detectdynamic and static hazards which may be caused by the circuit delays. Our approach is based on five logic values and the scheduled time. LOSIM has been implemented on a UN-3/160 workstation running Berkeley 4.2 UNIX, and the program is written in C language. Static RAM cell and asynchronous circuit are illustrated as an example.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• 제29권9호
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• pp.668-676
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• 2018

In satellite communications, a modulation technique with a low peak-to-average power ratio, high transmission efficiency, and low bit error rate(BER) is required, and differential amplitude and phase shift keying(DAPSK) modulation technique has been appraised as a technology that meets these requirements. However, because conventional DAPSK modulation uses a regular constellation diagram, the Euclidean distance between the symbols in the inner concentric circles of the constellation are quite short. Such a characteristic degrades the BER. In this paper, we propose a DAPSK system that uses an efficient constellation assignment to improve the performance of existing DAPSK systems and evaluate the performance of the proposed scheme. From the simulation results, we confirm that the proposed 16-DAPSK system achieves an signal-to-noise ratio gain of 0.8 dB over the conventional approach at a BER condition of $10^{-4}$ when the number of symbols used in the symbol detector of the receiver is 2.