• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.759-762
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• 1998

In this paper, a SL-DCVSL (static latched differential cascode voltage switch logic) circuit for the asynchronous pipeline is proposed. The proposed SL-DCVSL circuit is a slightly modified version of the DCVSL circuit, and used to improve the storage capability of the precharged functional blocks. The proposed SL-DCVSL has more robust storage characteristics compared to the conventional LDCVSL (latched DCVSL〔2〕). The operation of the proposed circuit is verified by simulating the asynchronous FIFO (First-In First-Out) structure.

• Ocean and Polar Research
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• v.23 no.2
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• pp.173-179
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• 2001

Parallel supercomputing is now a must for oceanographic numerical modelers. Most of today's parallel numerical schemes use synchronous algorithms, where some processors that have finished their tasks earlier than others must wait at synchronization points for correct computation. Hence, the load balancing is a crucial factor, however, it is, in general, difficult to achieve on heterogeneous workstation clusters. We devise an asynchronous algorithm that reduces the idle times of faster processors, and discuss application of the algorithm to some grid problems and implementation on a workstation cluster using Message Passing Interface (MPI).

• The Transactions of the Korean Institute of Electrical Engineers
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• v.33 no.2
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• pp.47-55
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• 1984

This paper is concerned with a computer-aided state assignment, that is, coding race-free internal states of asynchronous sequential circuits, and a method for minimizing the combinational network of asynchronous sequential circuits. The FORTRAN version of the peoposed algorithm results in race-free state assignments and reduction of the number of connections and gates with near minimal hardware cost. Some examples are designed by the proposed computer program to illustrate the algorithm in this paper. Finally, results are compared with those of the other methods.

• Proceedings of the Korean Information Science Society Conference
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• 2005.07a
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• pp.415-417
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• 2005

Core operations (e.9. TDMA scheduler, synchronized sleep period, data aggregation) of many proposed protocols for different layer of sensor network necessitate clock synchronization. Our Paper mingles the scheme of dynamic clustering and diffusion based asynchronous averaging algorithm for clock synchronization in sensor network. Our proposed algorithm takes the advantage of dynamic clustering and then applies asynchronous averaging algorithm for synchronization to reduce number of rounds and operations required for converging time which in turn save energy significantly than energy required in diffusion based asynchronous averaging algorithm.

• ETRI Journal
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• v.35 no.1
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• pp.35-40
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• 2013

Asynchronous ranging is one practical method to implement a locating system that provides accurate results. However, a locating system utilizing asynchronous ranging generates a large number of messages that cause transmission delays or failures and degrades the system performance. This paper proposes a novel approach for efficient congestion control in an asynchronous range-based locating system. The proposed method significantly reduces the number of messages generated during the reader discovery phase by eavesdropping on other transmissions and improves the efficiency of ranging by organizing the tags in a hierarchical fashion in the measurement phase. Our evaluation shows that the proposed method reduces the number of messages by 70% compared to the conventional method and significantly improves the success rate of ranging.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.6
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• pp.625-630
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• 2014

Asynchronous digital circuits working in military and space environments are often subject to the adverse effects of radiation faults. In this paper, we propose a new hardening technique against radiation faults. The considered digital system has the structure of DMR (Double Modular Redundancy), in which two sub-systems conduct the same work simultaneously. Based on the output feedback, the proposed scheme diagnoses occurrences of radiation faults and realizes immediate recovery to the normal behavior by overriding parts of memory bits of the faulty sub-system. As a case study, the proposed control scheme is applied to an asynchronous dual ring counter implemented in VHDL code.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.9
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• pp.1665-1675
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• 2007

This paper presents the problem of controlling asynchronous sequential machines in the presence of input disturbances, which may be also regarded as an adversary in a game theoretic setting. The main objective is to provide necessary and sufficient condition for the existence of a corrective controller that solves model matching problem of an asynchronous machine suffering from input disturbance. The existence condition can be stated in terms of a simple comparison of two skeleton matrices. The proposed controller eliminates the adversarial effect of input disturbance and makes the controlled machine mimic the behavior of a model in stable-state way. Whenever controller exists, algorithms for their design are outlined and demonstrated in a case study.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.4
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• pp.326-334
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• 1991

We propose an optical Asynchronous Transfer Mode(ATM) switching system using free-space optics and an output buffer memory. The distributor system in the switching fabric was analyzed using the Huygens-Fresnel principle and lens transformation. For monochromatic illumination, a pattern similar to the Fourier transform of the input distribution was observed across the output plane. A spatially broadened intensity distribution across the the output plane can be expected when the system is illminated with a partially coherent, quasimonochromatic beam. Spatially coherent pulses as short as 100fs can propagate through the distributor without severe spatial broadening.

• Journal of Electrical Engineering and Technology
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• v.2 no.3
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• pp.358-365
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• 2007

This paper deals with a novel solid state controller (NSSC) for parallel operated isolated asynchronous generators (IAG) feeding 3-phase 4-wire loads in constant power applications, such as uncontrolled pico hydro turbines. AC capacitor banks are used to meet the reactive power requirement of asynchronous generators. The proposed NSSC is realized using a set of IGBTs (Insulated gate bipolar junction transistors) based current controlled 4-leg voltage source converter (CC-VSC) and a DC chopper at its DC bus, which keeps the generated voltage and frequency constant in spite of changes in consumer loads. The complete system is modeled in MATLAB along with simulink and PSB (power system block set) toolboxes. The simulated results are presented to demonstrate the capability of isolated generating system consisting of NSSC and parallel operated asynchronous generators driven by uncontrolled pico hydro turbines and feeding 3-phase 4-wire loads.

• Journal of Sensor Science and Technology
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• v.26 no.3
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• pp.209-213
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• 2017

The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of high area overhead and high power consumption. This paper proposes a new NCL gate based on power gating structure. The proposed $4{\times}4$ NCL multiplier based on power gating structure is compared to the conventional NCL $4{\times}4$ multiplier and MTNCL(Multi-Threshold NCL) $4{\times}4$ multiplier in terms of speed, power consumption, energy and size using PTM 45 nm technology.