• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.12
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• pp.873-875
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• 2014

In this paper we describe an asynchronous MAC protocol with receiver-initiated duty cycling for energy-efficiency in wireless sensor networks(WSN). Legacy asynchronous MAC protocols, X-MAC and PW-MAC, has weaknesses which generates too many control packets and has data collision problem between multiple transmitters, respectively. Therefore, we propose a receiver-initiated asynchronous MAC protocol which generates control packets from transmitter to complement these disadvantages. Compared to the prior asynchronous duty cycling approaches of X-MAC and PW-MAC, the proposed protocol shows a improvement in energy-efficiency, throughput and latency from simulation results.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.4
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• pp.39-48
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• 2009

Asynchronous sequential machines, or clockless logic circuits, have several advantages over synchronous machines such as fast operation speed, low power consumption, etc. In this paper, we propose a novel robust controller for input/output asynchronous sequential machines with uncertain state transitions. Due to model uncertainties or inner failures, the state transition function of the considered asynchronous machine is not completely known. In this study, we present a formulation to model this kind of asynchronous machines ana using generalized reachability matrices, we address the condition for the existence of an appropriate controller such that the closed-loop behavior matches that of a prescribed model. Based on the previous research results, we sketch design procedure of the proposed controller and analyze the stable-state operation of the closed-loop system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.1-10
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• 2008

The problem of controlling asynchronous sequential machines is addressed in this paper. Corrective control means to make behavior of an asynchronous sequential machine equal to that of a given model. The main objective is to develope a corrective controller, especially when a model is given as nondeterministic, or a set of reference models. The structure of corrective control system for asynchronous sequential machines is addressed first, followed by description of nondeterministic models. Then, we propose a method for analyzing reachability of asynchronous machines and nondeterministic models. Proposed methods are demonstrated in an example.

• Journal of the Korean Institute of Intelligent Systems
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• v.25 no.2
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• pp.139-146
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• 2015

This paper presents the solution to model matching of switched asynchronous sequential machines by corrective control. We propose a model of switched asynchronous sequential machines, in which the system can have different dynamics of asynchronous machines governed by a pre-determined sequence of switching. The control objective is to derive a corrective control law so that the stable state behavior of the closed-loop system can match that of a prescribed model. A new skeleton matrix is defined to represent the reachability of the switched asynchronous machine, and a novel control scheme is presented that interweaves the switching signal and the corrective control procedure. A design algorithm for the proposed controller is illustrated in a case study.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.8
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• pp.1735-1740
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• 2005

SoC design integrates many IPs that operate at different frequencies and the use of the different clock for each IP makes the design the most effective one. An asynchronous FIFO is required as a kind of a buffer to connect IPs that are asynchronous. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, an asynchronous FIFO is designed to transfer data across asynchronous clock domains by using a valid bit scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the Bate level to compare with other FIFO scheme. The subject mater of this paper is under patent pending.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.1038-1041
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• 2005

In today's SoC design, most of IPs which use the different clock frequency from that of the bus require asynchronous FIFOs. However, in many cases, asynchronous FIFO is designed improperly and the cost of the wrong design is high. In this paper, a register-based asynchronous FIFO is designed to transfer data in asynchronous clock domains by using a valid bits scheme that eliminates the problem of the metastability and synchronization altogether. This FIFO architecture is described in HDL and synthesized to the gate level to compare with other FIFO scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.10a
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• pp.364-366
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• 2022

The web uses an asynchronous web method to provide various information having different processing speeds together. The asynchronous method has the advantage of being able to respond to other events even before the task is completed, but a typical crawler has difficulty collecting information provided asynchronously by collecting point-of-visit information on a web page. In addition, asynchronous web pages often do not change their web address even if the page content is changed, making it difficult to crawl. In this paper, we propose a web crawling algorithm considering asynchronous page movement by analyzing links in the web. With the proposed algorithm, it was possible to collect dictionary information on TTA terms that provide information asynchronously.

• The KIPS Transactions:PartC
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• v.10C no.3
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• pp.325-334
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• 2003

In stateless server, if an asynchronous cache invalidation scheme attempts to support local processing of read-only transaction in mobile client/sever database systems, a critical problem may occur ; the asynchronous invalidation reports provide no guarantees of waiting time for mobile transactions requesting commit. To solve this problem, the server in our algorithm broadcasts two kind of messages, asynchronous invalidation report to reduce transaction latency and periodic guide message to avoid the uncertainty of waiting time for the next invalidation report. The asynchronous invalidation report has its own sequence number and the periodic guide message has the sequence number of the most recently broadcast asynchronous invalidation report. A mobile client checks its cache validity by using the sequence numbers of these messages.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.7
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• pp.3152-3159
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• 2012

This paper presents the new instruction-level power model for an asynchronous processor. Until now, the various power models for estimating the power dissipation of embedded processor in SoC are proposed. Since all of them are target to the synchronous processors, the accuracy is questionable when we apply those power models to the asynchronous processor in SoC. To solve this problem, we present new power model for an asynchronous processor by reflecting the behavioral features of an asynchronous circuit. The proposed power model is verified using an implementation of asynchronous processor, A8051. The simulation results of the proposed model is compared with the measurement result of gate-level synthesized A8051. The proposed power model shows the accuracy of 90.7% and the simulation time for estimation the power consumption was reduced to 1,900 times.