• Journal of Educational Research in Mathematics
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• v.21 no.3
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• pp.239-259
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• 2011

This study investigated the elementary school students' ability on the algebraic reasoning as generalized arithmetic. It analyzed the written responses from 648 second graders, 688 fourth graders, and 751 sixth graders using tests probing their understanding of the properties of whole number operations. The result of this study showed that many students did not recognize the properties of operations in the problem situations, and had difficulties in applying such properties to solve the problems. Even lower graders were quite successful in using the commutative law both in addition and subtraction. However they had difficulties in using the associative and the distributive law. These difficulties remained even for upper graders. As for the associative and the distributive law, students had more difficulties in solving the problems dealing with specific numbers than those of arbitrary numbers. Given these results, this paper includes issues and implications on how to foster early algebraic reasoning ability in the elementary school.

• Journal of Elementary Mathematics Education in Korea
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• v.21 no.4
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• pp.643-662
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• 2017

The first appearance of the equations in elementary school mathematics is in the expression of the equal sign in the addition sentences without its definition. Most elementary school students have operational understanding of the equal sign in equations. Moreover, students' opportunities to have a clear concept of the properties of operations are limited because they are used implicitly in the textbooks. Based on this fact, it has been argued that it is necessary to introduce the properties of operations explicitly in terms of specific numbers and to deal with various types of equations for understanding a relational meaning of the equal sign. In this study, we use equations to represent the implicit properties of operations and the relational meaning of the equal sign in elementary school mathematics with respect to students' level of understanding. In addition, we give some explicit examples which show how to apply them to make efficient computations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.6
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• pp.1489-1497
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• 2018

Web application services have diversified. At the same time, research on intrusion detection is continuing due to the surge of cyber threats. Also, As a single-defense system evolves into multi-level security, we are responding to specific intrusions by correlating security events that have become vast. However, it is difficult to check the OS, service, web application type and version of the target system in real time, and intrusion detection events occurring in network-based security devices can not confirm vulnerability of the target system and success of the attack A blind spot can occur for threats that are not analyzed for problems and associativity. In this paper, we propose the validation of effectiveness for intrusion detection events using TF-IDF. The proposed scheme extracts the response traffics by mapping the response of the target system corresponding to the attack. Then, Response traffics are divided into lines and weights each line with an TF-IDF weight. we checked the valid intrusion detection events by sequentially examining the lines with high weights.

• Journal of KIISE
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• v.41 no.11
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• pp.871-877
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• 2014

Cache replacement algorithms have been developed in order to reduce miss counts. In modern processors, the performance gap between the processor and main memory has been increasing, creating a more important role for cache replacement policies. The Least Recently Used (LRU) policy is one of the most common policies used in modern processors. However, recent research has shown that the performance gap between the LRU and the theoretical optimal replacement algorithm (OPT) is large. Although LRU replacement has been proven to be adequate over and over again, the OPT/LRU performance gap is continuously widening as the cache associativity becomes large. In this study, we observed that there is a potential chance to improve cache performance based on existing LRU mechanisms. We propose a method that enhances the performance of the LRU replacement algorithm based on the access proportion among the lines in a cache set during a period of two successive replacement actions that make the final replacement action. Our experimental results reveals that the proposed method reduced the average miss rate of the baseline 512KB L2 cache by 15 percent when compared to conventional LRU. In addition, the performance of the processor that applied our proposed cache replacement policy improved by 4.7 percent over LRU, on average.

• Journal of KIISE:Computer Systems and Theory
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• v.37 no.5
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• pp.292-303
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• 2010

On-chip cache memories play an important role in both performance and energy consumption points of view in resource-constrained embedded systems by filtering many off-chip memory accesses. We propose a 2-level data cache architecture with a low energy-delay product tailored for the embedded systems. The L1 data cache is small and direct-mapped, and employs a write-through policy. In contrast, the L2 data cache is set-associative and adopts a write-back policy. Consequently, the L1 data cache is accessed in one cycle and is able to provide high cache bandwidth while the L2 data cache is effective in reducing global miss rate. To reduce the penalty of high miss rate caused by the small L1 cache and power consumption of address generation, we propose an ECP(Early Cache hit Predictor) scheme. The ECP predicts if the L1 cache has the requested data using both fast address generation and L1 cache hit prediction. To reduce high energy cost of accessing the L2 data cache due to heavy write-through traffic from the write buffer laid between the two cache levels, we propose a one-way write scheme. From our simulation-based experiments using a cycle-accurate simulator and embedded benchmarks, the proposed 2-level data cache architecture shows average 3.6% and 50% improvements in overall system performance and the data cache energy consumption.