• The Transactions of the Korea Information Processing Society
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• v.7 no.2
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• pp.520-528
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• 2000

he speed of microprocessor getting faster, the data transfer width between the microprocessor and the memory becomes a critical part to limit the system performance. So the study of the computer architecture with the high code density is cmerged. In this paper, a tentative Bi-Length Instruction Set Computer(BISC) that consists of 16 bit and 32 bit length instructions is proposed as the high code density 32 bit microprocessor architecture. The 32 bit BISC has 16 general purpose registers and two kinds of instructions due to the length of offset and the size of immediate operand. The proposed 32 bit BISC is implemented by FPGA, and all of its functions are tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit BISC are designed and verified. This paper also proves that the code density of 32 bit BISC is much higher than the one of traditional architecture, it accounts for 130~220% of RISC and 130~140% of CISC. As a consequence, the BISC is suitable for the next generation computer architecture because it needs less data transfer width. And its small memory requirement offers that it could be useful for the embedded microprocessor.

• Journal of Korea Multimedia Society
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• v.3 no.2
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• pp.192-200
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• 2000

8 bit and 16 bit microprocessors are widely used in the small sited control machine. The embedded microprocessors which is integrated on a single chip with the memory and I/O circuit must have simple hardware circuit and high code density. This paper proposes a 16 bit high code density EISC(Extendable Instruction Set Computer) microprocessor. SE1608 has 8 general purpose registers and 16 bit fixed length instruction set which has the short length offset and small immediate operand. By using an extend register and extend flag, the offset and immediate operand in instruction could be extended. SE1608 is implemented with 12,000 gate FPGA and all of its functions have been tested and verified at 8MHz. And the cross assembler, the cross C/C++compiler and the instruction simulator of the SE1608 have been designed and verified. This paper also proves that the code density$.$ of SE1608 shows 140% and 115% higher code density than 16 bit microprocessor H-8300 and MN10200 respectively, which is much higher than traditional microprocessors. As a consequence, the SE1608 is suitable for the embedded microprocessor since it requires less program memory to any other ones, and simple hardware circuit.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.1
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• pp.10-19
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• 1986

This is the last part of the four-part describing the development of a packet-switched computer communication network named the KORNET. In this paper we describe the design and implementation of the packet assembler/dissassembler (PAD) protocol for the asynchronous channel service, and of the network management softwares. The line processing module-B(LPMB) system supporting the asynchronous line includes a PAD protocol, a packet mode DTE/DCE protocol converting to the X.25 protocol, and the asynchronous receiver/transmitter(ART) software. The network management software is operated in master central processing module(MCPM) which includes virtual circuit management (VCM) managing the user channel, the routing management and the high level protocol for communication between the network management center (NMC) and the network node processor(NNP). In this paper, the design, implementation and operation of the softwares for the above service functions will be described in detail.

• Proceedings of the Korean Society of Crop Science Conference
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• 2022.10a
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• pp.28-28
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• 2022

This paper presents the first genome assemblies of Philippine mangoes that provide valuable reference for varietal improvement and genomic studies on mango and related fruit crops. WE sequenced whole genomes of3 species, Mangifera odorata (Huani), Mangifera altissima (Paho), and Mangifera indica 'Carabao' (Sweet Elena). 'Carabao' is the major export variety of the Philippines; Paho is identified as vulnerable by the IUCN Red List of Threatened Species; Huani has fruit sap acrid which is the primary defense mechanism against insects and birds. We used Falcon, a diploid aware -de novo assembler to assemble SMRT generated long-read sequences. Falcon-unzip was employed to phase the output assembly producing larger contig sets (primary contigs) and shorter contigs corresponding to haplotypes (haplotigs). Assembly statistics were generated by comparing the assembly to a reference genome, Tommy Atkins, using Quality Assessment Tool (QUAST). Moreover, the extent of duplication and completeness of gene content was measured using Benchmarking Universal Single-Copy Orthologs (BUSCO). Draft assemblies with high duplications were processed using Purge Haplotigs and Purge Dups to lessen duplications with minimal impact on genome completeness. De novo assemblies of Huani, Paho and 'Carabao' were then generated with primary contig sizes of 463.64 Mb, 508.95 Mb and 401.51 Mb respectively. These draft assemblies of Huani, Paho and 'Carabao' showed 96.90%, 95.17% and 99.07% complete BUSCOs respectively which is comparable to 'Tommy Atkins' genome (98.6%). Using two mango transcriptome data (pooled RNA-seq from different mango varieties and tissues), 91-96% or 24-30 million reads were successfully mapped back for each generated assembly indicating high degree of completeness. The results obtained demonstrated the highly contiguous, phased, and near complete genome assembly of three Philippine mango species for structural and functional annotation of gene units, especially those with economic importance.

• Journal of Biosystems Engineering
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• v.7 no.2
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• pp.18-29
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• 1983

A low cost and versatile data acquisition system for the field and laboratory use was developed by using a single board microcomputer. Data acquisition system based on a Z80 microprocessor was built, tested and modified to obtain the present functional system. The microcomputer developed consists of 6 kB ROM, 5 kB RAM, 6-seven segment LED display, 16-Hex. key and 8 command key board. And it interfaces with an 8 channel, 12 bits A/D converter, a microprinter, EPROM programmer for 2716, and RS232C interface to transfer data between the system and HP3000 mini-computer manufactured by Hewlett Packard Co., A software package was also developed, tested, and modified for the system. This package included drivers for the AID converter, LED display, key board, microprinter, EPROM programmer, and RS232c interface. All of these programs were written in 280 assembler language and converted to machine codes using a cross assembler by HP3000 computer to the system during modifying stage by data transferring unit of this system, then the machine language wrote to the EPROM by this EPROM programmer. The results are summarized as follows: 1. Measuring program developed was able to control the measuring intervals, No. of channels used, and No. of data, where the maximum measuring speed was 58.8 microsec. 2. Calibration of the system was performed with triangle wave generated by a function generator. The results of calibration agreed well to the test results. 3. The measured data was able to be written into EPROM, then the EPROM data was compared with original data. It took only 75 sec. for the developed program to write the data of 2 kB the EPROM. 4. For the slow speed measurements, microprinter instead of EPROM programmer proved to be useful. It took about 15 min. for microprinter to write the data of 2 kB. 5. Modified data transferring unit was very effective in communicating between the system and HP3000 computer. The required time for data transferring was only 1~2 min. 6. By using DC/DC converting devices such as 78-series, 79-series. and TL497 IC, this system was modified to convert the only one input power sources to the various powers. The available power sources of the system was DC 7~25 V and 1.8 A.

• Journal of Korean Society of Forest Science
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• v.79 no.2
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• pp.187-195
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• 1990

The following conclusions have been obtained with special reference to the walnut marketing system in Cheonwongun districts 1. The marketing channel of walnut in the producing areas was mainly depended on the individual selling by 89.58%. and sale through farmer's coops and forest owner's association by 10.42%, and share of walnut through fatmer's coops was 84.58%. 2. The market structure in assembling stage of walnut can be represented as oligopoly considering the market share of 86.26% derived by CR3 method. 3. Direct selling from producers to consumers would be recommendable to reduce marketing margin considering the 77.20% of sale's dependency on assembler-commisioner. 4. Two major reasons to follow the marketing channel of assembler-commissioner were the convieniency (45.00%) and dealing with small quantity of walnut (20.00%). Let the walnut producers follow the institutional marketing channels such as farmer's coops and forest owner s association, special actions including better conveniency, smaller quantity and the procedures should be improved. 5. Farmer's share of walnut was estimated as 54.93% and total marketing margin was 45.0% of which 36.70% destined to the retail stage. 6. The price index in November was the lowest(83.63) due to the flood and hunger sale and the index in April was the highest(115.74). To cope with the severe price fluctuation and to stabilize seasonal walnut price, sale's in advance, credit supply and provision of storage facilities must be considered in policy-making decision for forest farmers.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.5
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• pp.486-497
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• 2001

In this paper, we propose a new addressing mode, which can be used for programmable image processor to perform image-processing algorithms effectively. Conventional addressing modes are suitable for one-dimensional data processing such as voice, but the proposed addressing mode consider two-dimensional characteristics of image data. The proposed instruction for two-dimensional addressing requires two operands to specify a pixel and doesn't require any change of memory architecture. The proposed two-dimensional addressing mode for image processor has the following advantages. The proposed instruction combines several instructions to load a pixel data from an external memory to a register. Hence, the proposed instruction reduces required code size so that it satisfies high performance and low power requirements of image processor. In addition, it uses inherent two-dimensional characteristics of image data and offers user-friendly instruction to assembler programmer The proposed two-dimensional addressing mode is applicable to DSP, media processor, graphic device, and so on. In this paper, we propose a new concept of two-dimensional addressing mode and an efficient hardware implementation method of it.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.11-20
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• 1999

The data transfer width between the mocroprocessor and the memory comes to a critical part that limits system performance since the data transfer width has been as it was while the performance of a microprocessor is getting higher due to its continuous development in speed. And it is important that the memory should be in small size for the reduction of embedded microprocessor's price which is integrated on a single chip with the memory and IO circuit. In this paper, a mocroprocessor tentatively named as Extendable Instruction Set Computer(EISC) is proposed as the high code density 32 bit mocroprocessor architecture. The 32 bit EISC has 16 general purpose registers and 16 bit fixed length instruction which has the short length offset and small immediate operand. By using and extend register and extend flag, the offset and immediate operand could be extended. The proposed 32 bit EISC is implemented with an FPGA and all of its functions have been tested and verified at 1.8432MHz. And the cross assembler, the cross C/C++ compiler and the instruction simulator of the 32 bit EISC shows 140-220% and 120-140% higher code density than RISC and CISC respectively, which is much higher than any other traditional architectures. As a consequence, the EISC is suitable for the next generation computer architecture since it requires less data transfer width compared to any other ones. And its lower memory requirement will embedded microprocessor more useful.

• 한국해양학회지
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• v.22 no.3
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• pp.143-152
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• 1987

The digital data were obtained using Kennedy 9000 magnetic tape deck which was connected to the SMS960 side scan sonar during the field operations. The data of three consecutive survey tracks near Seongsan-po, Cheju were used for the development of this study. The softwares were mainly written in Fortran-77 using VAX 11/780 MINI-COMPUTER (CPU Memory; 4MB). The established mapping system consists of the pretreatment and the digital processing of seafloor image data. The pretreatment was necessary because the raw digital data format of the field magnetic tapes was not compatible to the VAX system. Therefore the raw data were read by the personal computer using the Assembler language and the data format was converted to IBM compatible, and next data were communicated to the VAX system. The digital processing includes geometrical correction for slant range, statistical analysis and cartography of the seafloor image. The sound speed in the water column was assumed 1,500 m/sec for the slant range correction and the moving average method was used for the signal trace smoothing. Histograms and cumulative curves were established for the statistical analysis, that was purposed to classify the backscattering strength from the sea-bottom. The seafloor image was displayed on the color screen of the TEKTRONIX 4113B terminal. According to the brief interpretation of the result image map, rocky and sedimentary bottoms were very well discriminated. Also it was shown that the backscattered acoustic pressurecorrelateswith the grain size and sorting of surface sediments.

• Journal of Korean Society of Forest Science
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• v.71 no.1
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• pp.1-8
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• 1985

In the study, the log pricing process by region and marketing agencies was surveyed in order to analyze the domestic timber marketing situation, and to propose improvements. The results obtained show that the market channel configuration for domestic timber is simple compared with that for the agricultural products. The log felling contractor is the lead agency in the stumpage market because of the lack of market information of most forest owners. However, the log assembler, who has ample funds, seized leadership in the market channel because most felling contractors, deal only with small timber quantities, and are usually short of funds. Also the variety of log scaling methods is a serious factor confusing domestic timber marketing. Therefore, the following steps are proposed; 1) the provision of market information to forest owners, 2) the institutional control of felling contractors, 3) the establishment of cooperative log collection centers, 4) the improvement of log quality.