• 전자공학회논문지A
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• 제33A권2호
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• pp.163-172
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• 1996

In reconfiguration of systolic arrays, a potential disadvantage is that in the PRESENCE of consective faulty PE's logically connected PE's may be far apart, requiring the reduction of clock speed and thus reducing throughput of the array. Thus it is fundamental tokeep locality of interconnections as high as possible even after reconfiguration and to make reconfiguration implemented in the simple routing devices. However requirements of locality and simplicity mean that reconfiguring capability is limited. This paper deals iwth the issue of developing efficient method for reconfiguration of 2-D systolic arrays which can be achieved high reconfiguration rate, with the two conditions satisfying using concept of pseudo faulty processing element. Applying this concept to reconfiguration of systolic array, we have found similar condition. The simulation shows that recomfiguration rates are 97%, 84% when N faults ocurs on the N$\times$N array n case of N=5, 8 respectively.

• 한국마린엔지니어링학회:학술대회논문집
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• 한국마린엔지니어링학회 2006년도 전기학술대회논문집
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• pp.169-170
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• 2006

The main purpose of this study is to develop a program for sound field visualization system which gets noise signals in microphones array for incoming noise signals and it uses to operate noise signals and to store data in multi-channel FFT and is consisted to visualize noise signals with a image which is got by camera in center of array by using beamforming algorithm of the array signal processing.

• 전자공학회논문지B
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• 제30B권7호
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• Journal of Information Processing Systems
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• 제13권1호
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• pp.83-94
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• 2017

Near-field source localization algorithms are very sensitive to sensor gain/phase response errors, and so it is important to calibrate the errors. We took into consideration the uniform linear array and are proposing a blind calibration algorithm that can estimate the directions-of-arrival and range parameters of incident signals and sensor gain/phase responses jointly, without the need for any reference source. They are estimated separately by using an iterative approach, but without the need for good initial guesses. The ambiguities in the estimations of 2-D electric angles and sensor gain/phase responses are also analyzed in this paper. We show that the ambiguities can be remedied by assuming that two sensor phase responses of the array have been previously calibrated. The behavior of the proposed method is illustrated through simulation experiments. The simulation results show that the convergent rate is fast and that the convergent precision is high.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.269-272
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• 2001

In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2022년도 추계학술대회
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• pp.349-350
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• 2022

최근 인공지능 분야는 자율주행, 로봇 및 스마트 통신등 다양한 분야에 응용되고 있다. 현재의 인공지능 응용분야는 파이썬을 기반으로 한 tensor flow를 이용하는 소프트웨어 방식을 이용하고 있으며, 프로세서로는 PC의 그래픽 카드 내부에 존재하는 GPU (Graphics Processing Unit)를 이용하고 있다. 본 연구에서는 HDL (Hardware Description Language)을 이용하여 FPGA (Field Programmable Gate Array)를 기반으로 한 신경망 회로를 이용하여 인공지능 시스템을 구현하였으며, 본 논문에서는 FPGA기반 인공지능 시스템을 구현하기 위한 영상인식 시스템에 대해 발표하고자 한다.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 추계학술대회
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• pp.371-374
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• 2009

본 논문은 대한민국 해군의 차세대호위함인 FFX(Fast Frigate eXperimental)에 장착/운용되는 LAS(Line Array Sensor, 예인배열형센서)로부터 A,B,C 그룹 수중음향신호의 시리얼 데이터를 입력받아 약속된 Protocol로 Packing하여, 고속 데이터통신과 Optic-fiber채널 장거리 전송이 가능한 SFM(Serial FPDP Module)을 통해 신호처리단으로 실시간 전송하는 센서데이터입출력처리보드의 설계/제작 및 시험에 관해 논한다. VME 6U크기의 한정된 보드 공간을 고려하여 Freescale사의 PowerPC계열인 MPC8265 CPU와, FIFO등의 외부디바이스를 줄이고 자체시뮬레이션 데이터생성등을 위해 Altera사의 CycloneIII 계열 FPGA등을 사용하여 설계하고, 실시간 데이터 전송을 보장하며 각종 Device Driver, Peripheral Controller등의 Library를 제공하는 RTOS인 VxWorks를 Porting하여 소프트웨어를 개발하였다.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1985년도 추계학술발표회 논문집
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• pp.148-152
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• 1985

• Journal of information and communication convergence engineering
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• 제12권3호
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• pp.140-144
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• 2014

A general linearly constrained adaptive array is examined in the weight vector space to illustrate the array performance with respect to the gain factor. A narrowband linear adaptive array is implemented in a coherent signal environment. It is shown that the gain factor in the general linearly constrained adaptive array has an effect on the linear constraint gain of the conventional linearly constrained adaptive array. It is observed that a variation of the gain factor of the general linearly constrained adaptive array results in a variation of the distance between the constraint plane and the origin in the translated weight vector space. Simulation results are shown to demonstrate the effect of the gain factor on the nulling performance.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1999년도 제14차 학술회의논문집
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• pp.262-265
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• 1999

This paper describes a new method for object extraction necessary for image tracking systems. The extraction method which this paper proposes here is that an M-array is set between a camera and the object and the obtained image including the object and M-array is pro-cessed for extracting the object. The image processing utilizes a characteristic of M-array which is robust to noise. When an M-array is overlapped on the object in background image, the object woud have a part of M-array, which is detected by use of partial correlation between the mosaic image of M-array and the standard M-array. Thus the shape and position of the object are extracted by extracting a common domain of width of high correlation value. Experiments are carried out by using an actual photo of Kumamoto city taken from an airplane as background, and by use of a rectangular and circular object. The results of experiment show a wide application of this method for practical image tracking systems.