• Title/Summary/Keyword: array processing

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Improvement of reconfiguration rate using pseudo faulty processing elements on the single track 2-D systolic array (의사결함처리요소를 이용한 단일트랙 이차원 시스토릭 어레이에서 재구성율의 향상)

  • 신동석;우종호
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.2
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    • pp.163-172
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    • 1996
  • In reconfiguration of systolic arrays, a potential disadvantage is that in the PRESENCE of consective faulty PE's logically connected PE's may be far apart, requiring the reduction of clock speed and thus reducing throughput of the array. Thus it is fundamental tokeep locality of interconnections as high as possible even after reconfiguration and to make reconfiguration implemented in the simple routing devices. However requirements of locality and simplicity mean that reconfiguring capability is limited. This paper deals iwth the issue of developing efficient method for reconfiguration of 2-D systolic arrays which can be achieved high reconfiguration rate, with the two conditions satisfying using concept of pseudo faulty processing element. Applying this concept to reconfiguration of systolic array, we have found similar condition. The simulation shows that recomfiguration rates are 97%, 84% when N faults ocurs on the N$\times$N array n case of N=5, 8 respectively.

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Sound Field Visualization System Development for Reducing Noise of Marine Equipment (조선기자재 소음저감을 위한 음장가시화법 개발)

  • Kim, Chang-Nam;Sun, Jin-Suk;Wang, Ji-Suk;Kim, Ue-Kan
    • Proceedings of the Korean Society of Marine Engineers Conference
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    • 2006.06a
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    • pp.169-170
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    • 2006
  • The main purpose of this study is to develop a program for sound field visualization system which gets noise signals in microphones array for incoming noise signals and it uses to operate noise signals and to store data in multi-channel FFT and is consisted to visualize noise signals with a image which is got by camera in center of array by using beamforming algorithm of the array signal processing.

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A Study on VLSI-Oriented 2-D Systolic Array Processor Design for APP (Algebraic Path Problem) (VLSI 지향적인 APP용 2-D SYSTOLIC ARRAY PROCESSOR 설계에 관한 연구)

  • 이현수;방정희
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.7
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    • pp.1-13
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    • 1993
  • In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

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Joint Estimation of Near-Field Source Parameters and Array Response

  • Cui, Han;Peng, Wenjuan
    • Journal of Information Processing Systems
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    • v.13 no.1
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    • pp.83-94
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    • 2017
  • Near-field source localization algorithms are very sensitive to sensor gain/phase response errors, and so it is important to calibrate the errors. We took into consideration the uniform linear array and are proposing a blind calibration algorithm that can estimate the directions-of-arrival and range parameters of incident signals and sensor gain/phase responses jointly, without the need for any reference source. They are estimated separately by using an iterative approach, but without the need for good initial guesses. The ambiguities in the estimations of 2-D electric angles and sensor gain/phase responses are also analyzed in this paper. We show that the ambiguities can be remedied by assuming that two sensor phase responses of the array have been previously calibrated. The behavior of the proposed method is illustrated through simulation experiments. The simulation results show that the convergent rate is fast and that the convergent precision is high.

A Study on the Design of Format Converter for Pixel-Parallel Image Processing (픽셀-병렬 영상처리에 있어서 포맷 컨버터 설계에 관한 연구)

  • 김현기;김현호;하기종;최영규;류기환;이천희
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.269-272
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    • 2001
  • In this paper we proposed the format converter design and implementation for real time image processing. This design method is based on realized the large processor-per-pixel array by integrated circuit technology in which this two types of integrated structure is can be classify associative parallel processor and parallel process with DRAM cell. Layout pitch of one-bit-wide logic is identical memory cell pitch to array high density PEs in integrate structure. This format converter design has control path implementation efficiently, and can be utilized the high technology without complicated controller hardware. Sequence of array instruction are generated by host computer before process start, and instructions are saved on unit controller. Host computer is executed the pixel-parallel operation starting at saved instructions after processing start

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A Realization of FPGA-based Image Recognition System (FPGA기반 영상인식 시스템 구현)

  • Young Yun
    • Proceedings of the Korean Institute of Navigation and Port Research Conference
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    • 2022.11a
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    • pp.349-350
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    • 2022
  • Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. In this work, we developed an FPGA-based (Field Programmable Gate Array) AI system , and report on image recognition system to realize the AI system.

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A Design of LAS data processing board using PowerPC and VxWorks (PowerPC 및 VxWorks를 이용한 예인배열센서 데이터처리보드 개발)

  • Lim, Byeong-Seon;Kim, Young-Kil
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2009.10a
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    • pp.371-374
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    • 2009
  • This Paper deal with a design, making a prtotype and test methods of Real-time towed Line Array Sensor Data processing board for fast data communication and long range transmission with SFM(Serial FPDP Module) through Optic-fiber channel. The LAS A,B,C group Data from towed line array sensor which is installed in FFX(Fast Frigate eXperimental) of Korean Navy is packed a previously agreed protocol and transmitted to the Signal processing unit. Consider the limited space of VME 6U size, LAS Data processing board is designed with MPC8265 PowerPC Controller of Freescale for main system control and Altera's CycloneIII FPGA for sensor data packing, self-test simulation data generation, S/W FIFO et cetera. LAS Data processing board have VxWorks, the RTOS(Real Time Operating System) that present many device drivers, peripheral control libraries on board for real-time data processing.

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Optimum Array Processing with Variable Linear Constraint

  • Chang, Byong Kun
    • Journal of information and communication convergence engineering
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    • v.12 no.3
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    • pp.140-144
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    • 2014
  • A general linearly constrained adaptive array is examined in the weight vector space to illustrate the array performance with respect to the gain factor. A narrowband linear adaptive array is implemented in a coherent signal environment. It is shown that the gain factor in the general linearly constrained adaptive array has an effect on the linear constraint gain of the conventional linearly constrained adaptive array. It is observed that a variation of the gain factor of the general linearly constrained adaptive array results in a variation of the distance between the constraint plane and the origin in the translated weight vector space. Simulation results are shown to demonstrate the effect of the gain factor on the nulling performance.

A Method for Extracting Shape and Position of an Object using Partial M-array

  • Kaba, K.;Kashiwagi, H.
    • 제어로봇시스템학회:학술대회논문집
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    • 1999.10a
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    • pp.262-265
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    • 1999
  • This paper describes a new method for object extraction necessary for image tracking systems. The extraction method which this paper proposes here is that an M-array is set between a camera and the object and the obtained image including the object and M-array is pro-cessed for extracting the object. The image processing utilizes a characteristic of M-array which is robust to noise. When an M-array is overlapped on the object in background image, the object woud have a part of M-array, which is detected by use of partial correlation between the mosaic image of M-array and the standard M-array. Thus the shape and position of the object are extracted by extracting a common domain of width of high correlation value. Experiments are carried out by using an actual photo of Kumamoto city taken from an airplane as background, and by use of a rectangular and circular object. The results of experiment show a wide application of this method for practical image tracking systems.

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