• The Transactions of the Korea Information Processing Society
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• v.5 no.8
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• pp.1972-1984
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• 1998

• Journal of Sensor Science and Technology
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• v.17 no.6
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• pp.406-413
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• 2008

We have been implemented simple statistical pattern recognition methods for harmful gases classification using gas sensors array fabricated by MEMS (Micro Electro Mechanical System) technology. The performance of pattern recognition method as a gas classifier is highly dependent on the choice of pre-processing techniques for sensor and sensors array signals and optimal classification algorithms among the various classification techniques. We carried out pre-processing for each sensor's signal as well as sensors array signals to extract features for each gas. We adapted simple statistical pattern recognition algorithms, which were PCA (Principal Component Analysis) for visualization of patterns clustering and MLR (Multi-Linear Regression) for real-time system implementation, to classify harmful gases. Experimental results of adapted pattern recognition methods with pre-processing techniques have been shown good clustering performance and expected easy implementation for real-time sensing system.

• Transactions of Materials Processing
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• v.14 no.5 s.77
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• pp.477-481
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• 2005

Wafer scale micro mirror array with high surface quality for small form factor (SFF) optical pick-up was fabricated by micro UV-molding. To replicate micro mirror array for SFF optical pick-up, a high- precision mold was fabricated using micro-machining technology. Wafer scale micro mirror array was UV-molded using the mold and then the process was optimized experimentally. The surface flatness and roughness of UV-molded micro mirror array were measured by white light scanning interferomety system and analyzed the transcribing characteristics. Finally, the measured flatness of UV-molded micro mirror away for SFF optical pick-up, which was fabricated in the optimum processing condition, was less than 70nm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

• Journal of Information Processing Systems
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• v.16 no.4
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• pp.774-783
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• 2020

For the issue of subsurface target localization by reverse projection, a new approach of target localization with different distances based on symmetric sub-array multiple-input multiple-output (MIMO) radar is proposed in this paper. By utilizing the particularity of structure of the two symmetric sub-arrays, the received signals are jointly reconstructed to eliminate the distance information from the steering vectors. The distance-independent direction of arrival (DOA) estimates are acquired, and the localizations of subsurface targets with different distances are realized by reverse projection. According to the localization mechanism and application characteristics of the proposed algorithm, the grid zooming method based on spatial segmentation is used to optimize the locaiton efficiency. Simulation results demonstrate the effectiveness of the proposed localization method and optimization scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.702-708
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• 2000

In this paper, we designed one-dimensional VLSI array with optimal pipeline period for high speed processing fractal image compression. The algorithm is derived which is suitable for VLSI array from axed block partition algorithm. Also the algorithm satisfies high quality of image and high compression-ratio. The designed VLSI array has optimal pipeline relied because the required processing time of PEs is distributed as same as possible. As this result, we can improve the processing speed up to about 3 times. The number of input/output pins can be reduced by sharing the input/output and arithmetic unit of the domain blocks and the range blocks.

• KIPS Transactions on Software and Data Engineering
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• v.6 no.4
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• pp.185-192
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• 2017

In various fields of science, 2-dimensional array data is being generated actively as a result of measurements and simulations. Although various query processing techniques for array data are being studied, the problem of finding similar regions, whose sizes are not known in advance, in 2-dimensional array has not been addressed yet. Therefore, in this paper, we propose an efficient method for finding regions with similar element values, whose size is larger than a user-specified value, for a given 2-dimensional array data. The proposed method, for each pair of elements in the array, expands the corresponding two regions, whose initial size is 1, along the right and down direction in stages, keeping the shape of the two regions the same. If the difference between the elements values in the two regions becomes larger than a user-specified value, the proposed method stops the expansion. Consequently, the proposed method can find similar regions efficiently by accessing only those parts that are likely to be similar regions. Through theoretical analysis and various experiments, we show that the proposed method can find similar regions very efficiently.

• The Transactions of the Korea Information Processing Society
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• v.6 no.5
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• pp.1219-1224
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• 1999

This paper derived Montgomery's parallel algorithms for modular multiplication based on Walter's and Iwamura's method, and compared data dependence graph of each parallel algorithm. Comparing the result, Walter's parallel algorithm has small computational index in data dependence graph, so it is selected and used to computed spatial and temporal pipelining diagrams with each projection direction for designing expansible bit-level systolic array. We also evaluated internal operation of proposed expansible systolic array C++ language.

• Proceedings of the Korean Information Science Society Conference
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• 1998.10a
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• pp.691-693
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• 1998

A parallel processing systolic array reduces execution time of the Back-propagation ANN. But, systolic array must be designed whenever the number of neurons in the ANN differ. To use the systolic array which is aready designed ad a fixed size VLSI chip, partition of the problem size systolic array must be performed. This paper presents a design method of the fixed size systolic array for the Back-propagation algorthm using LSGP and LPGS partion method

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.373-376
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• 2001

This paper has been studied a real-time video frame data processing control that used the linear systolic array for motion estimation. The proposed data control processing provides to the input data into the multiple processor array unit(MPAU) from search area and reference block data. The proposed data control architecture has based on two slice band for input data processing. And it has no required external control logic blocks for input data as like reference block or search area data.