• Journal of KIISE:Computer Systems and Theory
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• v.35 no.7
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• pp.327-331
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• 2008

Optimal Extension Fields (OEFs) are finite fields of a special form which are very useful for software implementation of elliptic curve cryptosystems. Bailey and Paar introduced efficient OEF arithmetic algorithms including the $p^ith$ powering operation, and an efficient algorithm to construct OEFs for cryptographic use. In this paper, we give a counterexample where their $p^ith$ powering algorithm does not work, and show that their OEF construction algorithm is faulty, i.e., it may produce some non-OEFs as output. We present improved algorithms which correct these problems, and give improved statistics for the number of OEFs.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.540-543
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• 2013

This paper describes an implementation of a unified ALU on multi-core GPGPU based on SIMT architecture. Our unified ALU can operate conditional branch instructions, data movement instructions, integer arithmetic instructions and floating-point arithmetic instructions. Since multi-core GPGPU contains a lot of ALU for parallel processing of various types, the main point of this paper is to design the minimum size ALU by unifying similar processing of each operations on circit level. All instrunctions were tested by making a test program. And we compare this results with results of CPU operations to verify our ALU. Our unified ALU's gate size is approximately 20,000 and the maximum operation frequency is 430MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.3
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• pp.439-446
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• 1998

This paper presents design of SD adder and PD adder on Multi-Valued Logic. For implementing of Multi-valued logic circuits we use Current-mode CMOS circuits and also use Voltage-mode CMOS circuits partially. The proposed arithmetic circuits was estimated by SPICE simulation. At the SD(Signed-Digit) number presentation applying Multi-Valued logic the carry propagation is always limited to one position to the left this number presentation allows fast parallel operation. The addition method that add M operands using PD( positive digit number) is effective not only for the realization of the high-speed compact arithmetic circuit, but also for the reduction of the interconnection in the VLSI processor. therefor, if we use PD number representation, the high speed processor can be implementation.

• The Journal of Information Technology
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• v.9 no.4
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• pp.49-55
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• 2006

In this paper, a new fragile watermarking algorithm for digital image is presented, which makes resolving the security and forgery problem of the digital image to be possible. The most suitable watermarking method that verifies the authentication and integrity of the digital image is the Wong's method, which invokes the hash function (MD5). The algorithm is safe because this method uses the hash function of the cryptology. The operations such as modulus, complement, shift, bitwise exclusive-or, bitwise inclusive-or are necessary for calculating the value of hash function. But, in this paper, an Arithmetic encoding method that only includes the multiplication operation is adopted. This technique prints out accumulative probability interval, which is obtained by multiplying the input symbol probability interval. In this paper, the initial probability interval is determined according to the value of the key, and the input sequence of the symbols is adjusted according to the key value so that the accumulative probability interval will depend on the key value. The integrity of the algorithm has been verified by experiment. The PSNR is above the 51.13db and the verifying time is $1/3{\sim}1/4$ of the verifying time of using the hash function (MD5), so, it can be used in the real-time system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.1
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• pp.101-106
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• 2020

This paper relates with the VS-QE-MMA (Varying Stepsize-Quantized Error-MMA) based on the varying stepsize for improving the equalization performance in the QE-MMA adaptive equalization algorithm that is possible to reducing the intersymbol interference occurred at channel. The SE-MMA use the high-order statistics of transmitted signal and sign of error signal. The QE-MMA was appeared for the H/W implementation easiness substitutes the multiplication and substraction into the shift and substraction in the updating the tap coefficient based on the power-of-two operation of error signal magnitude. The QE-MMA gives degradation of equalization performance due to the such simplification of arithmetic operation. For improving this problem, the propose algorithm, namely VS-QE-MMA, applies the varying stepsize of the nonlinear transformation of error signal. It was confirmed by simulation that the VS-QE-MMA gives better performance than current QE-MMA in the same channel and signal to noise ratio. As a result of simulation, the VS-QE-MMA has more better performance in the every performance index, and it was also confirmed that the varying stepsize effect can be obtained in the greater than 10dB of signal to noise ratio.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3C
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• pp.176-184
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• 2005

In this paper, we implemented an Elliptic Curve Cryptography(ECC) processor for Digital Transmission Contents Protection (DTCP), which is a standard for protecting various digital contents in the network. Unlikely to other applications, DTCP uses ECC algorithm which is defined over GF(p), where p is a 160-bit prime integer. The core arithmetic operation of ECC is a scalar multiplication, and it involves large amount of very long integer modular multiplications and additions. In this paper, the modular multiplier was designed using the well-known Montgomery algorithm which was implemented with CSA(Carry-save Adder) and 4-level CLA(Carry-lookahead Adder). Our new ECC processor has been synthesized using Samsung 0.18 m CMOS standard cell library, and the maximum operation frequency was estimated 98 MHz, with the size about 65,000 gates. The resulting performance was 29.6 kbps, that is, it took 5.4 msec to process a 160-bit data frame. We assure that this performance is enough to be used for digital signature, encryption and decryption, and key exchanges in real time environments.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.2
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• pp.224-229
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• 2005

Generally, genetic algorithm (GA) has too much time and space complexity when it is running in the typical processor. Therefore, we are forced to use the high-performance and expensive processor by this reason. It also works as a barrier to implement real device, such a small mobile robot, which is required only simple rules. To solve this problem, this paper presents and proposes enhanced processor-architecture for the faster GA processing. A typical processor architecture can be enhanced and specialized by two approaches: one is a sorting network, the other is a residue number system (RNS). A sorting network can improve the time complexity of which needs to compare the populations' fitness. An RNS can reduce the magnitude of the largest bit that dictates the speed of arithmetic operation. Consequently, it can make the total logic size smaller and innovate arithmetic operation speed faster.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.1
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• pp.159-168
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• 2010

In the recent years, power analysis attacks were widely investigated, and so various countermeasures have been proposed. In the case of block ciphers, masking methods that blind the intermediate results in the algorithm computations(encryption, decryption, and key-schedule) are well-known. The type conversion of masking is unavoidable since Boolean operation and Arithmetic operation are performed together in block cipher. Messerges proposed a masking type conversion algorithm resistant general power analysis attack and then it's vulnerability was reported. We present that some of exiting attacks have some practical problems and propose a new power analysis attack on Messerges's algorithm. After we propose the strengthen DPA and CPA attack on the masking type conversion algorithm, we show that our proposed attack is a practical threat as the simulation results.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.8 no.2
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• pp.15-21
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• 2008

This paper discuss the sequential digital logic systems and arithmetic operation algorithms which is the important material in computer architecture using analysis and synthesis which is based on extension logic for binary logic over galois fields. In sequential digital logic systems, we construct the moore model without feedback sequential logic systems after we obtain the next state function and output function using building block T-gate. Also, we obtain each algorithms of the addition, subtraction, multiplication, division based on the finite fields mathematical properties. Especially, in case of P=2 over GF($P^m$), the proposed algorithm have a advantage which will be able to apply traditional binary logic directly.The proposed method can construct more efficiency digital logic systems because it can be extended traditional binary logic to extension logic.

• Journal of the Korea Society of Computer and Information
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• v.17 no.12
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• pp.49-60
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• 2012

In this paper, we propose a hardware design for correction of barrel distortion using the nearest coordinates in the corrected image. Because it applies the nearest distance on corrected image rather than adjacent distance on distorted image, the picture quality is improved by the image whole area, solve the staircase phenomenon in the exterior area. But, because of additional arithmetic operation using design of bilinear interpolation, required arithmetic operation is increased. Look up table(LUT) structure is proposed in order to solve this, coordinate rotation digital computer(CORDIC) algorithm is applied. The results of the synthesis using Design compiler, the design of implementing all processes of the interpolation method with the hardware is higher than the previous design about the throughput, In case of the rear camera, the design of using LUT and hardware together can reduce the size than the design of implementing all processes with the hardware.