• Journal of Biomedical Engineering Research
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• v.26 no.4
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• pp.223-230
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• 2005

This paper presents a new approach to investigate spatial correlation between independent components of brain alpha activity in functional magnetic resonance imaging (fMRI) and electroencephalography (EEG). To avoid potential problems of simultaneous fMRI and EEG acquisitions in imaging pure alpha activity, data from each modality were acquired separately under a 'three conditions' setup where one of the conditions involved closing eyes and relaxing, thus making it conducive to generation of alpha activity. The other two conditions -- eyes open in a lighted room or engaged in a mental arithmetic task, were designed to attenuate alpha activity. Using a Mixture Density Independent Component Analysis (MD-ICA) that incorporates flexible non-linearity functions into the conventional ICA framework, we could identify the spatiotemporal components of fMRI activations and EEG activities associated with the alpha rhythm. Then, the sources of the individual EEG alpha activity component were localized by a Maximum Entropy (ME) method that is specially designed to find the most probable dipole distribution minimizing the localization error in sense of LMSE. The resulting active dipoles were spatially transformed to 3D MRls of the subject and compared to fMRI alpha activity maps. A good spatial correlation was found in the spatial distribution of alpha sources derived independently from fMRI and EEG, suggesting the proposed method can localize the cortical areas responsible for generating alpha activity successfully in either fMRI or EEG. Finally a functional connectivity analysis was applied to show that alpha activity sources of both modalities were also functionally connected to each other, implying that they are involved in performing a common function: 'the generation of alpha rhythms'.

• Journal of the Korea Society of Computer and Information
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• v.12 no.4
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• pp.33-42
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• 2007

Accurate predictions of software release times, and estimation of the reliability and availability of a software product require quantification of a critical element of the software testing process : test coverage. This model called Enhanced non-homogeneous poission process(ENHPP). In this paper, exponential coverage and S-shaped model was reviewed, proposes the Kappa coverage model, which maked out efficiency application for software reliability. Algorithm to estimate the parameters used to maximum likelihood estimator and bisection method, model selection based on SSE statistics and Kolmogorov distance, for the sake of efficient model, was employed. From the analysis of mission time, the result of this comparative study shows the excellent performance of Burr coverage model rather than exponential coverage and S-shaped model using NTDS data. This analysis of failure data compared with the Kappa coverage model and the existing model(using arithmetic and Laplace trend tests, bias tests) is presented.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.79-90
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• 2000

In this paper, a high-performance floating point unit, which is suitable for high-performance superscalar microprocessors and supports IEEE 754 standard, is designed. Floating-point arithmetic unit (AU) supports all denormalized number processing through hardware, while eliminating the additional delay time due to the denormalized number processing by proposing the proposed gradual underflow prediction (GUP) scheme. Contrary to the existing fixed-radix implementations, floating-point divide/square root unit adopts a new architecture which determines variable length quotient bits per cycle. The new architecture is superior to the SRT implementations in terms of performance and design complexity. Moreover, sophisticated exception prediction scheme enables precise exception to be implemented with ease on various superscalar microprocessors, and removes the stall cycles in division. Designed floating-point AU and divide/square root unit are integrated with and instruction decoder, register file, memory model and multiplier to form a floating-point unit, and its function and performance is verified.

• Journal of the Korean Data and Information Science Society
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• v.21 no.2
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• pp.279-289
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• 2010

In this study, we propose a simple statistical model for determining the admission or discharge of 668 patients with a chief complaint of dyspnea. For this, we use 11 explanatory variables which are chosen to be important by clinical experts among 55 variables. As a modification process, we determine the discharge interval of each variable by the kernel density functions of the admitted and discharged patients. We then choose the optimal model for determining the discharge of patients based on the number of explanatory variables belonging to the corresponding discharge intervals. Since the numbers of the admitted and discharged patients are not balanced, we use, as the criteria for selecting the optimal model, the arithmetic mean of sensitivity and specificity and the harmonic mean of sensitivity and precision. The selected optimal model predicts the discharge if 7 or more explanatory variables belong to the corresponding discharge intervals.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.6A
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• pp.640-647
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• 2006

This paper describes a design of AES-based CCMP(Counter mode with CBC-MAC Protocol) core for IEEE 802.11i wireless LAN security. To maximize the performance of CCMP core, two AES cores are used, one is the counter mode for data confidentiality and the other is the CBC node for authentication and data integrity. The S-box that requires the largest hardware in ARS core is implemented using composite field arithmetic, and the gate count is reduced by about 27% compared with conventional LUT(Lookup Table)-based design. The CCMP core was verified using Excalibur SoC kit, and a MPW chip is fabricated using a 0.35-um CMOS standard cell technology. The test results show that all the function of the fabricated chip works correctly. The CCMP processor has 17,000 gates, and the estimated throughput is about 353-Mbps at 116-MHz@3.3V, satisfying 54-Mbps data rate of the IEEE 802.11a and 802.11g specifications.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.1
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• pp.109-113
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• 2011

Recently, according to the development of ubiquitous computing, the u-GIS which not only used in u-Transport, u-Care, u-Fun, u-Green, u-Business, u-Government, and u-City but also used to provides various spatial information such as the location of user is being the core technology of the ubiquitous computing environment. In this paper, we implemented an mobile spatio-temporal Query Processing Systems for handling the Spatio-Temporal Data in mobile equipment.The mobile spatio-temporal Query Processing Systems provides the spatio-temporal data type and the spatio-temporal operator that is expanded by the spatial data type and the spatial operator from OepenGIS "Simple Feature Specification for SQL". It supports arithmetic coding compression techniques that is considered with a spatio-temporal data specific character. It also provides the function of data cashing for improving the importation and exportation of the spatio-temporal data between a embedded spatio-temporal DBMS and u-GIS server.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.12A
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• pp.1009-1018
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• 2003

A new fading channel estimation technique is proposed for an OFDM based modem In the ITS system. The algorithm is based on the transfer function extraction of the channel using the pilot signals and compensated the channel preceding the equalization. The newly derived algorithm is division-free arithmetic operations allows the faster circuit operation and the smaller circuit size. Proposed techniques compensate firstly the distortion which is generated at fading channels and secondly eliminate inter-symbol interference. All algorithms are suitability estimated and improved for a system implementation using digital circuits. As the results, the circuit size is reduced by 20% of the conventional design and achieved about 10% performance improvement at low SNR under 10dB in case of ITS system adapted 16-QAM mode.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.8
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• pp.1471-1479
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• 2017

This paper describes a design of RSA public-key cryptography processor supporting key length of 2,048 bits. A modular multiplier that is core arithmetic function in RSA cryptography was designed using word-based Montgomery multiplication algorithm, and a modular exponentiation was implemented by using Left-to-Right (LR) binary exponentiation algorithm. A computation of a modular multiplication takes 8,386 clock cycles, and RSA encryption and decryption requires 185,724 and 25,561,076 clock cycles, respectively. The RSA processor was verified by FPGA implementation using Virtex5 device. The RSA cryptographic processor synthesized with 100 MHz clock frequency using a 0.18 um CMOS cell library occupies 12,540 gate equivalents (GEs) and 12 kbits memory. It was estimated that the RSA processor can operate up to 165 MHz, and the estimated time for RSA encryption and decryption operations are 1.12 ms and 154.91 ms, respectively.

• The Transactions of the Korean Institute of Power Electronics
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• v.22 no.3
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• pp.240-248
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• 2017

This paper describes the development of a powertrain for a 20 kW experimental electric vehicle using a surface-mounted permanent magnet synchronous motor (SPMSM) and its application to a test vehicle. Two 10 kW SPMSMs are used in the powertrain, and two-level inverters are developed by using IGBTs to derive these motors. To control the SPMSM, a control board based on a TMS320F28335 DSP module, which has fast arithmetic function and floating point operator, is used. We develop a 100 V/40 A battery pack, which includes $32{\times}4$ LiFePO4 battery cells using commercial BMS. A commercial on-board charger with 220 V (AC) input and 100 V (DC) and 18 A output is used to charge the battery pack. The performance of the developed vehicle, such as acceleration availability, maximum speed, and maximum power, is estimated based on vehicle dynamics and verified through experiments.

• Journal of Advanced Navigation Technology
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• v.8 no.2
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• pp.190-196
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• 2004

The development of a new hardware structure which can implement the viterbi algorithm efficiently is required for applications such as a software radio because the viterbi algorithm, which is an error correction code function for the second and the third generation of mobile communication, needs a lot of arithmetic operations. The length of K in the viterbi algorithm different from each standard, for examples, K=7 in case of IS-95 standard and GSM standard, and K=9 in case of WCDMA and CDMA2000. In this paper, we propose a new hardware structure of an adaptive viterbi decoder which can decode the constraint length in K=3~9 and the data rate in 1/2 ~ 1/3. Prototyping results targeted to Altera Cyclon EPIC20F400C8, shows that the proposed hardware structure needs maximum 19,276 logic elements and power dissipation of 222.6 mW.