• Title/Summary/Keyword: area overhead

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Temperature and Load Change behavior of Overhead Conductor under loading current due to Forest Fire (산불에 의한 활선선로의 이도변화 거동)

  • Kim, Byung-Geol;Jang, Young-Ho;Kim, Shang-Shu;Han, Se-Won
    • Proceedings of the KIEE Conference
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    • 2009.07a
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    • pp.1295_1296
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    • 2009
  • The authors have published several technical reports on the deterioration of conductor due to forest fire in series so far. This is because even we have been experiencing hundreds of forest fires every year, no systematic research on conductor which is very vulnerable to fire have been fulfilled. This paper describes the sag-tension behavior of conductor under loading current normally when only partial area of a long conductor is exposed to fire. Temperaures of Overhead Conductor were different with measurement position. When the partial area of conductor was heated up to $500^{\circ}C$, 20 % of permanent tension loss was observed. This results in the increase of sag of 1.5 m when span is 300 m. The other results will be presented in the text.

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Tensile Characteristics of ACSR Overhead Lines located in seaside (해안지역 ACSR 가공지선의 기계적 특성)

  • Jang, T.I.;Kang, J.W.;Lee, D.I.;Jang, I.C.
    • Proceedings of the KIEE Conference
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    • 2001.07c
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    • pp.1709-1711
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    • 2001
  • The remaining life of ACSR(Aluminum Conductor Steel Reinforced) wires exposed to the atmosphere for a long period relies on the extent of deterioration caused by environmental factors such as atmospheric corrosion, galvanic corrosion, crevice corrosion and fatigue corrosion. We investigated the tensile characteristics of ACSR wires in a coastal area through several mechanical tests, and analyzed the constituents of them using SEM(scanning electron microscope). Test samples are parts of ACSR 97[$mm^2$] overhead transmission lines in that area. The result shows that ACSR wires exposed to salt may lead to rapid mechanical deterioration.

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Temperature and Load Change behavior of Overhead Conductor under loading current due to Forest Fire (통전 중 산불에 노출된 가공송전선의 온도 및 장력 변화 거동)

  • Kim, Byung-Geol;Jang, Young-Ho;Kim, Shang-Shu;Han, Se-Won
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.22 no.4
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    • pp.366-371
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    • 2009
  • The authors have published several technical reports on the deterioration of conductor due to forest fire in series so far. This is because even we have been experiencing hundreds of forest fires every year, no systematic research on conductor which is very vulnerable to fire have been fulfilled. This paper describes the sag-tension behavior of conductor under loading current normally when only partial area of a long conductor is exposed to fire. Temperatures of Overhead Conductor were different with measurement position. When the partial area of conductor was heated up to $500^{\circ}C$, 20 % of permanent tension loss was observed. This results in the increase of sag of 1.5 m when span is 300 m. The other results will be presented in the text.

Improvement of cell area overhead for crosstalk prevention design flow by using clock shielding (크로스토크 방지 기술을 적용한 칩 제작기법에서의 클럭 넷 쉴드 처리에 의한 셀 면적 오버헤드 개선)

  • Lee, Jun-Seop;Song, Jae-Hoon;Kim, Min-Chul;Kim, Ki-Bum;Park, Sung-Ju
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.445-446
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    • 2008
  • With the semiconductor industry evolving into the deep sub-micron (DSM) era, the crosstalk effects on interconnect lines of a chip have increasingly caused a major bottleneck for design closure. In this paper, we propose an effective design guide line to reduce cell area overhead without crosstalk noise violations by using crosstalk prevention flow with clock shielding.

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Test Point Insertion with Control Point by Greater Use of Existing Functional Flip-Flops

  • Yang, Joon-Sung;Touba, Nur A.
    • ETRI Journal
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    • v.36 no.6
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    • pp.942-952
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    • 2014
  • This paper presents a novel test point insertion (TPI) method for a pseudo-random built-in self-test (BIST) to reduce the area overhead. Recently, a new TPI method for BISTs was proposed that tries to use functional flip-flops to drive control test points instead of adding extra dedicated flip-flops for driving control points. The replacement rule used in a previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip-flops. This paper proposes a logic cone analysis-based TPI approach to overcome the limitations. Logic cone analysis is performed to find candidate functional flop-flops for replacing dedicated flip-flops. Experimental results indicate that the proposed method reduces the test point area overhead significantly with minimal loss of testability by replacing the dedicated flip-flops.

Multiple ASR for efficient defense against brute force attacks (무차별 공격에 효과적인 다중 Address Space Randomization 방어 기법)

  • Park, Soo-Hyun;Kim, Sun-Il
    • The KIPS Transactions:PartC
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    • v.18C no.2
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    • pp.89-96
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    • 2011
  • ASR is an excellent program security technique that protects various data memory areas without run-time overhead. ASR hides the addresses of variables from attackers by reordering variables within a data memory area; however, it can be broken by brute force attacks because of a limited data memory space. In this paper, we propose Multiple ASR to overcome the limitation of previous ASR approaches. Multiple ASR separates a data memory area into original and duplicated areas, and compares variables in each memory area to detect an attack. In original and duplicated data memory areas variables are arranged in the opposite order. This makes it impossible to overwrite the same variables in the different data areas in a single attack. Although programs with Multiple ASR show a relatively high run-time overhead due to duplicated execution, programs with many I/O operations such as web servers, a favorite attack target, show 40~50% overhead. In this paper we develop and test a tool that transforms a program into one with Multiple ASR applied.

Low-Cost CRC Scheme by Using DBI(Data Bus Inversion) for High Speed Semiconductor Memory (고속반도체 메모리를 위한 DBI(Data Bus Inversion)를 이용한 저비용 CRC(Cyclic Redundancy Check)방식)

  • Lee, Joong-Ho
    • Journal of IKEEE
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    • v.19 no.3
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    • pp.288-294
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    • 2015
  • CRC function has been built into the high-speed semiconductor memory device in order to increase the reliability of data for high-speed operation. Also, DBI function is adopted to improve of data transmission speed. Conventional CRC(ATM-8 HEC code) method has a significant amounts of area-overhead(~XOR 700 gates), and processing time(6 stage XOR) is large. Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC calculations. In this paper, we propose a CRC method for low cost and high speed memory, which was improved 92% for area-overhead. For low-cost implementation of the CRC scheme by the DBI function it was supplemented by data bit error detection rate. And analyzing the error detection rate were compared with conventional CRC method.

A Wire-overhead-free Reset Propagation Scheme for Millimeter-scale Sensor Systems

  • Lee, Inhee;Bang, Suyoung;Kim, Yejoong;Kim, Gyouho;Sylvester, Dennis;Blaauw, David;Lee, Yoonmyung
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.4
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    • pp.524-533
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    • 2017
  • This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a $180-{\mu}m$ CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages.

Delay Insensitive Asynchronous Circuit Design Based on New High-Speed NCL Cells (새로운 고속의 NCL 셀 기반의 지연무관 비동기 회로 설계)

  • Kim, Kyung Ki
    • Journal of Korea Society of Industrial Information Systems
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    • v.19 no.6
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    • pp.1-6
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    • 2014
  • The delay-insensitive Null Convention Logic (NCL) asynchronous design as one of innovative asynchronous logic design methodologies has many advantages of inherent robustness, power consumption, and easy design reuses. However, transistor-level structures of conventional NCL gate cells have weakness of low speed, high area overhead or high wire complexity. Therefore, this paper proposes a new high-speed NCL gate cells designed at transistor level for high-speed, low area overhead, and low wire complexity. The proposed NCL gate cells have been compared to the conventional NCL gates in terms of circuit delay, area and power consumption.

Power Frequency Magnetic Field Reduction Method for Residents in the Vicinity of Overhead Transmission Lines Using Passive Loop

  • Lee, Byeong-Yoon;Myung, Sung-Ho;Cho, Yeun-Gyu;Lee, Dong-Il;Lim, Yun-Seog;Lee, Sang-Yun
    • Journal of Electrical Engineering and Technology
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    • v.6 no.6
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    • pp.829-835
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    • 2011
  • A power frequency magnetic field reduction method using passive loop is presented. This method can be used to reduce magnetic fields generated within the restricted area near transmission lines by alternating current overhead transmission lines. A reduction algorithm is described and related equations for magnetic field reduction are explained. The proposed power frequency magnetic field reduction method is applied to a scaled-down transmission line model. The lateral distribution of reduction ratio between magnetic fields before and after passive loop installation is calculated to evaluate magnetic field reduction effects. Calculated results show that the passive loop can be used to cost-effectively reduce power frequency magnetic fields in the vicinity of transmission lines generated by overhead transmission lines, compared with other reduction methods, such as active loop, increase in transmission line height, and power transmission using underground cables.