• 한국통신학회논문지
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• 제32권9C호
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• pp.913-921
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• 2007

프로세서에 따라 수행 가능한 코드를 생성하는 retargetable 컴파일러와 성능 프로파일러는 어플리케이션에 최적화된 프로세서 디자인에 있어 필수적이다. 본 논문은 ADL (Architecture Description Language)에 기반한 architecture exploration 방법을 제시한다. 어플리케이션 프로그램에서 얻어낸 정보로부터 인스트럭션 합성과 프로세서 구조를 최적화 하였다. 어플리케이션에서 많이 사용되는 연산과 레지스터 사용에 대한 정보는 프로세서 최적화를 위해 사용되었다. 시스템의 효용성을 보이기 위해 JPEG 인코더에 대한 architecture exploration을 수행하였다. 제안된 방법을 사용해 설계된 ASIP은 초기 프로세서에 비해 약 1.97배의 성능을 가지는 것으로 측정되었다.

• Asia pacific journal of information systems
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• 제28권4호
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• pp.240-257
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• 2018

In today's turbulent business landscape, a firm's ability to explore new IT capabilities and exploit current ones is essential for enabling organizational agility and achieving high organizational performance. We propose IT exploration and exploitation as two critical organizational learning processes that are essential for gaining and sustaining competitive advantages. However, it remains unclear how the emerging cloud-based IT architecture affects an organization's ability to explore and exploit its IT capabilities. We conceptualize modularity and virtuality as two critical dimensions of emerging cloud-based IT architecture and investigate how they affect IT exploration and exploitation. We test our hypotheses using data obtained from our field survey of IT managers. We find that modularity is positively associated with both exploration and exploitation whereas virtuality is positively associated with exploration, but not with exploitation. We also find that the effect of modularity on exploitation is stronger than its effect on exploration.

• Journal of Astronomy and Space Sciences
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• 제41권1호
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• pp.43-60
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• 2024

Korea Pathfinder Lunar Orbiter (KPLO) is South Korea's first space exploration mission, developed by the Korea Aerospace Research Institute. It aims to develop technologies for lunar exploration, explore lunar science, and test new technologies. KPLO was launched on August 5, 2022, by a Falcon-9 launch vehicle from cape canaveral space force station (CCSFS) in the United States and placed on a ballistic lunar transfer (BLT) trajectory. A total of four trajectory correction maneuvers were performed during the approximately 4.5-month trans-lunar cruise phase to reach the Moon. Starting with the first lunar orbit insertion (LOI) maneuver on December 16, the spacecraft performed a total of three maneuvers before arriving at the lunar mission orbit, at an altitude of 100 kilometers, on December 27, 2022. After entering lunar orbit, the commissioning phase validated the operation of the mission mode, in which the payload is oriented toward the center of the Moon. After completing about one month of commissioning, normal mission operations began, and each payload successfully performed its planned mission. All of the spacecraft operations that KPLO performs from launch to normal operations were designed through the system operations design process. This includes operations that are automatically initiated post-separation from the launch vehicle, as well as those in lunar transfer orbit and lunar mission orbit. Key operational procedures such as the spacecraft's initial checkout, trajectory correction maneuvers, LOI, and commissioning were developed during the early operation preparation phase. These procedures were executed effectively during both the early and normal operation phases. The successful execution of these operations confirms the robust verification of the system operation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권2호
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• pp.75-79
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• 2009

A system-on-a-chip communication architecture has a significant impact on the performance and power consumption of modern multi-processors system-on-chips (MPSoCs). However, customization of such architecture for a specific application requires the exploration of a large design space. Thus, system designers need tools to rapidly explore and evaluate communication architectures. In this paper we present the method for application-specific low-power bus architecture synthesis at system-level. Our paper has two contributions. First, we build a bus power model of AMBA AXI bus communication architecture. Second, we incorporate this power model into a low-power architecture exploration algorithm that enables system designers to rapidly explore the target bus architecture. The proposed exploration algorithm reduces power consumption by 20.1% compared to a maximally connected reduced matrix, and the area is also reduced by 20.2% compared to the maximally connected reduced matrix.

• ETRI Journal
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• 제38권6호
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• pp.1240-1249
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• 2016

With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration.

• 한국해양공학회지
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• 제22권4호
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• pp.72-77
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• 2008

General aspects of deepwater petroleum exploration and production were identified and related technical challenges were addressed. Historical perspectives, insight, processes, and engineering applications are reviewed to enhance the design capability of the domestic offshore industry. The technical challenges and unique aspects of deepwater exploration and production were identified. The assessment of deepwater exploration, drilling, and production systems is a key stage for performing the front end engineering design (FEED). The global trends in deepwater development, including the feasibility for Korea, were reviewed.

• 대한전자공학회논문지SD
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• 제45권4호
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• pp.78-85
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• 2008

네트워크 SoC 칩을 대상으로 SystemC를 이용한 High-level 설계 방법을 연구하였다. 실제 Verilog RTL 모델과 비교하여 깊이있는 Architecture 구조탐색과 정확한 SystemC 모델 cycle 검증을 토대로 하여 High-level 설계를 강조할 것이다. 대다수 High-level 설계와 접근방법과 다르게, SystemC 모델과 Verilog RTL 모델의 성능을 비교해 보고, SystemC-based platform을 검증하기 위해 On-chip test board 측정 데이터를 이용하였다. 이 논문에서는 High-level 설계기법이 RTL 모델과 같은 정확성을 얻을 수 있을 뿐만 아니라, RTL 모델보다 100배 이상 빠른 시뮬레이션 속도를 달성할 수 있음을 보여 주었다. 그리고, 아키텍처 구조탐색을 통해서 시스템 성능하락의 원인을 파악하고, 대안을 찾아보았다.

• 한국통신학회논문지
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• 제35권12B호
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• pp.1758-1765
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• 2010

본 논문은 임베디드 코어의 설계 계층을 이용한 아키텍처 탐색 방법론을 제안한다. 제안된 방법은 다양한 설계 검증과 계층적인 설계 수준에 따른 성능 측정을 고려한 체계적인 아키텍처 탐색을 수행한다. 성능 측정 도구는 설계 모듈에 관련 있는 성능 데이터를 가진 프로파일을 생성한다. 프로파일 생성기는 설계 모듈과 성능 매개변수에 대한 연관 규칙을 얻기 위해 데이터마이닝을 수행한다. 프로파일 생성기의 추론 엔진은 다음 탐색 과정의 설계 성능을 향상시키는 새로운 연관 규칙을 얻는다. 제안된 아키텍처 탐색 방법론의 효율성을 확인하기 위해 JPEG 인코더, Chen-DCT, FFT의 어플리케이션에 대한 아키텍처 탐색을 수행하였다. 제안된 방법을 이용하여 설계된 임베디드 코어는 MIPS R3000의 초기 임베디드 코어에 비해 평균 60.8%의 수행 사이클 감소를 보인다.

• 한국컴퓨터정보학회:학술대회논문집
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• 한국컴퓨터정보학회 2014년도 제49차 동계학술대회논문집 22권1호
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• pp.1-4
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• 2014

Although physical modeling synthesis is becoming more and more efficient in rich and natural high-quality sound synthesis, its high computational complexity limits its use in portable devices. This constraint motivated research of single-instruction multiple-data many-core architectures that support the tremendous amount of computations by exploiting massive parallelism inherent in physical modeling synthesis. Since no general consensus has been reached which grain sizes of many-core processors and memories provide the most efficient operation for sound synthesis, design space exploration is conducted for seven processing element (PE) configurations. To find an optimal PE configuration, each PE configuration is evaluated in terms of execution time, area and energy efficiencies. Experimental results show that all PE configurations are satisfied with the system requirements to be implemented in portable devices.

• 건축사
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• 통권592호
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• pp.140-151
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• 2018