• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2006년도 춘계학술대회
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• pp.183-186
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• 2006

Reduction of optical losses in crystalline silicon solar cells by surface modification is one of the most important issues of silicon photovoltaics. Porous Si layers on the front surface of textured Si substrates have been investigated with the aim of improving the optical losses of the solar cells, because an anti-reflection coating and a surface passivation can be obtained simultaneously in one process. We have demonstrated the feasibility of a very efficient porous Si AR layer, prepared by a simple, cost effective, electrochemical etching method. Silicon p-type CZ (100) oriented wafers were textured by anisotropic etching in sodium carbonate solution. Then, the porous Si layer were formed by electrochemical etching in HF solutions. After that, the properties of porous Si in terms of morphology, structure and reflectance are summarized. The surface morphology of porous Si layers were investigated using SEM. The formation of a porous Si layer about $0.1{\mu}m$ thick on the textured silicon wafer result in an effective reflectance coefficient $R_{eff}$ lower than 5% in the wavelength region from 400 to 1000nm. Such a surface modification allows improving the Si solar cell characteristics.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.26-31
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• 2023

We investigated the impact of NF₃ / H₂O remote plasma dry cleaning conditions on the SiO₂ etching rate at different preparation states during the fabrication of ultra-large-scale integration (ULSI) devices. This included consideration of factors like Si crystal orientation prior to oxidation and three-dimensional structures. The dry cleaning process were carried out varying the parameters of pressure, NF₃ flow rate, and H₂O flow rate. We found that the pressure had an effective role in controlling anisotropic etching when a thin SiO₂ layer was situated between Si₃N₄ and Si layers in a multilayer trench structure. Based on these observations, we would like to provide further guidelines for implementing the dry cleaning process in the fabrication of semiconductor devices having 3D structures.

• 대한전기학회논문지
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• 제43권6호
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• pp.1036-1038
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• 1994

In this paper, a silicon piezoresistive accelerometer is designed and fabricated using a silicon direct bonded wafer. The accelerometer consists of a seismic mass and four cantilevers, and is fabricated mainly by the anisotropic etching method using EPW as an etchant. The measured sensitivity and the resonant frequency are 0.02 mV/V.g and 3.4 kHz, respectively. The nonlinearity is less than $\pm$0.3% of the full scale of the output.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1963-1967
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• 1996

This paper describes the analysis, design, and silicon-fabrication of a fluidic proportional amplifier, which is the most important element of fluidic logic circuits. First, FEM(finite element method) analyses were performed, using the Fluent computational fluid dynamics program, and design geometries were optimized. Then, a $40\;{\mu}m$-deep amplifier was fabricated in silicon using anisotropic dry etching.

• 한국산학기술학회:학술대회논문집
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• 한국산학기술학회 2000년도 추계학술대회
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• pp.185-193
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• 2000

이방성 습식 식각을 이용하여 멤브레인을 제작하기 위하여 KOH-IPA의 식각액을 사용하여 단결정 실리콘 기판을 이방성으로 식각을 하고, 각 용액에 대한 식각 특성을 관찰하였다. 식각률은 식각액의 온도와 농도에 의존하며, 패턴 형성 방향과 식각액의 농도에 따라 식각 형태가 다르게 나타났다. 패턴은 Primary Flat에 45°로 기울여 형성되었으며 20wt·% KOH 80℃ 이상에서는 U-groove, 그 이하의 온도와 농도에서는 V-groove 식각 형태를 관찰할 수 있었다. 각 면에 대한 식각률 차이에 의해서 생기는 Hillock은 온도와 농도가 높아짐에 따라 줄어들었고, 재식각을 퉁하여 현저하게 줄어듦을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.241-241
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• 2008

Macrofore formation in silicon and other semiconductors using electrochemical etching processes has been, in the last years, a subject of great attention of both theory and practice. Its first reason of concern is new areas of macropore silicone applications arising from microelectromechanical systems processing (MEMS), membrane techniques, solar cells, sensors, photonic crystals, and new technologies like a silicon-on-nothing (SON) technology. Its formation mechanism with a rich variety of controllable microstructures and their many potential applications have been studied extensively recently. Porous silicon is formed by anodic etching of crystalline silicon in hydrofluoric acid. During the etching process holes are required to enable the dissolution of the silicon anode. For p-type silicon, holes are the majority charge carriers, therefore porous silicon can be formed under the action of a positive bias on the silicon anode. For n-type silicon, holes to dissolve silicon is supplied by illuminating n-type silicon with above-band-gap light which allows sufficient generation of holes. To make a desired three-dimensional nano- or micro-structures, pre-structuring the masked surface in KOH solution to form a periodic array of etch pits before electrochemical etching. Due to enhanced electric field, the holes are efficiently collected at the pore tips for etching. The depletion of holes in the space charge region prevents silicon dissolution at the sidewalls, enabling anisotropic etching for the trenches. This is correct theoretical explanation for n-type Si etching. However, there are a few experimental repors in p-type silicon, while a number of theoretical models have been worked out to explain experimental dependence observed. To perform ordered macrofore formaion for p-type silicon, various kinds of mask patterns to make initial KOH etch pits were used. In order to understand the roles played by the kinds of etching solution in the formation of pillar arrays, we have undertaken a systematic study of the solvent effects in mixtures of HF, N-dimethylformamide (DMF), iso-propanol, and mixtures of HF with water on the macrofore structure formation on monocrystalline p-type silicon with a resistivity varying between 10 ~ 0.01 $\Omega$ cm. The etching solution including the iso-propanol produced a best three dimensional pillar structures. The experimental results are discussed on the base of Lehmann's comprehensive model based on SCR width.

• 한국세라믹학회지
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• 제35권8호
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• pp.813-818
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• 1998

A simple method to measure the elastic modulus E and Poisson's ratio v of diamod-like carbon (DLC) films deposited on Si wafer was suggested. Using the anisotropic etching technique of Si we could make the edge of DLC overhang free from constraint of Si substrate. DLC film is chemically so inert that we could not on-serve any surface damage after the etching process. The edge of DLC overhang free from constraint of Si substrate exhibited periodic sinusoidal shape. By measuring the amplitude and the wavelength of the sinu-soidal edge we could determine the stain of the film required to adhere to the substrate. Since the residual stress of film can be determine independently by measurement of the curvature of film-substrate com-posite we could calculated the biaxial elastic modulus E/(1-v) using stress-strain relation of thin films. By comparing the biaxial elastic modulus with the plane-strain modulus E/(1-{{{{ { v}^{2 } }}) measured by nano-in-dentation we could further determine the elastic modulus and Poisson's ratio independently. This method was employed to measure the mechanical properties of DLC films deposited by {{{{ { {C }_{6 }H }_{6 } }} rf glow discharge. The was elastic modulus E increased from 94 to 169 GPa as the {{{{ { V}_{ b} / SQRT { P} }} increased from 127 to 221 V/{{{{ {mTorr }^{1/2 } }} Poisson's ratio was estimated to be abou 0.16∼0.22 in this {{{{ { V}_{ b} / SQRT { P} }} range. For the {{{{ { V}_{ b} / SQRT { P} }} less than 127V/{{{{ {mTorr }^{1/2 } }} where the plastic deformation can occur by the substrate etching process however the present method could not be applied.

• 마이크로전자및패키징학회지
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• 제8권4호
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• pp.17-23
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• 2001

3차원 홀 센서는 두 개의 수평 자계($\chi$, y성분) 검출부와 한 개의 수직 자계(z 성분) 검출부를 갖는다. 종래의 3차원 홀 센서는 일반적으로 $B_{z}$에 대한 감도가 $B_\chi, B_y$에 대한 감도의 약 1/10정도에 그친다. 본 연구에서는 새로운 구조를 갖는 3차원 홀 센서를 제안하였다. 이방성 식각을 이용하여 트랜치를 형성함으로써 감도를 약 6배 증가시켰다. 또한 자속을 집속시키기 위하여 웨이퍼 후면에 강자성체 박막을 증가시킴으로써 $B_{z}$에 대한 감도를 $B_\chi, B_y$에 대한 감도의 약 80% 정도로 증가시켰다. 전류 3 mA를 인가했을 때, Ni/Fe 박막을 증착하여 제작된 센서의 감도는 $B_\chi, B_y$, B$_{z}$ 에 대하여 각각 120.1 mV/T, 111.7 mV/T, 그리고 95.3 mV/T로 측정되었다. 센서의 선형성을 오차가 $\pm$3%로 우수하였다.

• 한국전기전자재료학회논문지
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• 제26권11호
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• pp.841-845
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• 2013

We give a textured front on silicon wafer for high-efficiency solar cells by using micro contact printing method which uses PDMS (polydimethylsiloxane) silicon rubber as a stamp and SAM (self assembled monolayer)s as an ink. A random pyramidal texturing have been widely used for a front-surface texturing in low cost manufacturing line although the cell with random pyramids on front surface shows relatively low efficiency than the cell with inverted pyramids patterned by normal optical lithography. In the past two decades, the micro contact printing has been intensively studied in nano technology field for high resolution patterns on silicon wafer. However, this promising printing technique has surprisingly never applied so far to silicon based solar cell industry despite their simplicity of process and attractive aspects in terms of cost competitiveness. We employ a MHA (16-mercaptohexadecanoic acid) as an ink for Au deposited $SiO_2/Si$ substrate. The $SiO_2$ pattern which is same as the pattern printed by SAM ink on Au surface and later acts as a hard resist for anisotropic silicon etching was made by HF solution, and then inverted pyramidal pattern is formed after anisotropic wet etching. We compare three textured surface with different morphology (random texture, random pyramids and inverted pyramids) and then different geometry of inverted pyramid arrays in terms of reflectivity.

• 한국광학회지
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• 제16권2호
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• pp.113-120
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• 2005

LCD-BLU(liquid crystal device-back light unit)에 사용되는 도광판의 미세 산란패턴을 만드는 새로운 방법으로서, 실리콘 웨이퍼의 비등방 식각에 의해 자연적으로 형성되는 3차원 결정면 구조를 이용하는 방법을 제안하였다. 실리콘 3차원 결정면을 갖는 도광판과 프리즘 시트의 원판을 설계 및 제작하였고, casting 공정을 통해 PDMS 재질로 복제된 도광판을 제작하여 특성을 분석하였다. 측정 결과, 기존 인쇄형 도광판에 비해 실리콘피라미드 패턴의 도광판이 $10\%$ 증가된 정면 휘도 효율을 가질 수 있음을 실험적으로 검증하였다.