• International Journal of Highway Engineering
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• v.15 no.6
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• pp.41-47
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• 2013

PURPOSES : The purpose of this study is about noise which is generated from roads and is consist of irregular frequency variation from low frequency to various band. The existing methods of noise reduction are sound barrier that uses insulation material and absorbing material or have applied passive technology of noise reduction by devices. The total frequency band is needed to apply active noise control. METHODS : In this study applies to the field of road traffic environment, signal processing controller and various analog signal input/output, the amplifier module is based on parallel-core embedded processor designed. DSP performs the control algorithm of the road traffic noise. Noise sources in the open space performance of evaluation were applied. In this study, controller of active signal processor was designed based on the module of audio input/output and main controller of embedded process. The controller of active signal processor operates noise reduction algorithm and performance tests of noise reduction in inside and outside environment were executed. RESULTS : The signal processing controller with OMAP-L137 parallel-core processors as the center, DSP processors in the active control operations dealt with quickly. To maximize the operation speed of an object and ARM processor is external function keys and display for functions and evaluating the performance management system was designed for the purpose of the interface. Therefore the reduction of road traffic noise has established an electronic controller-based noise reduction. CONCLUSIONS : It is shown that noise reduction is effective in the case of pour tonal sound and complex tonal sound below 500Hz by appling to Fx-LMS.

• Journal of Ocean Engineering and Technology
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• v.24 no.1
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• pp.166-171
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• 2010

In this paper, the front-end of a digital receiver with a 25 kHz carrier frequency, 5 kHz symbol rate, and any excess-bandwidth is designed using two basic facts. The first is known as the uniform sampling theorem, which states that the sampled sequence might not suffer from aliasing even if its sampling rate is lower than the Nyquist sampling rate if the analog signal is a bandpass one. The other fact is that if the sampling rate is 4 times the center frequency of the sampled sequence, the front-end processing complexity can be dramatically reduced due to the half of the sampled sequence to be multiplied by zero in the demixing process. Furthermore, the designed front-end is simplified by introducing sub-filters and sub-sampling sequences. The designed front-end is composed of an A/D converter, which takes samples of a bandpass filtered signal at a 20 kHz rate; a serial-to-parallel converter, which converts a sampled bandpass sequence to 4 parallel sub-sample sequences; 4 sub-filter blocks, which act as a frequency shifter and lowpass filter for a complex sequence; 4 synchronized switches; and 2 adders. The designed front-end dramatically reduces the computational complexity by more than 50% for frequency shifting and lowpass filtering operations since a conventional front-end requires a frequency shifting and two lowpass filtering operations to get one lowpass complex sample, while the proposed front-end requires only four filtering operation to get four lowpass complex samples, which is equivalent to one filtering operation for one sample.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.116-121
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• 2005

To realize the tap coefficient of a finite impulse response(FIR) filter or the twiddle factor of a fast Fourier transform(FFT) using a current-mode analog circuit, a high accurate current-attenuator circuit is needed This paper introduces an accuracy enhancement technique in the current-mode signal processing. First of all, the DC of set-current error in a conventional current-attenuator using a gate-ratioed orient mirror circuit is analyzed and then, the current-attenuator circuit with a negligibly small DC offset-current error is introduced. The circuit consists of N-output current mirrors connected in parallel with me another. The output current of the circuit is attenuated to 1/N of the input current. On the basis of the Kirchhoff current law, the current scale ratio is determined simply by the number of the current mirrors in the N-current mirrors connected in parallel. In the proposed current-attenuator circuit the scale accuracy is limited by the ac gain error of the current mirror. Considering that a current mirror has a negligibly small ac gain error, the attainable maximum scale accuracy is theoretically -80[dB] to the input current.

• 전자공학회논문지 IE
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• v.47 no.4
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• pp.18-27
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• 2010

This paper is designed the efficient Data Acquisition System for an vibration of rotatory machines. The Data Acquisition System is consist of the analog logic having signal filer and amplifier, and digital logic with ADC, DSP, FPGA and FIFO memory. The vibration signal of rotatory machines acquired from sensors is controlled by the FPGA device through the analog logic and is saved to FIFO memory being converted analog to digital signal. The digital signal process is performed by the DSP using the vibration data in FIFO memory. The vibration factor of the rotatory machinery analysis and diagnosis is defined the RMS, Peak to Peak, average, GAP, FFT of vibration data and digital filtering by DSP, and is need to follow as being happened the event of vibration and make an application to an warning system. It takes time to process the several analysis step of all vibration data and the event follow, also special event. It should be continuously performed the data acquisition and the process, however during processing the input signal the DSP can not be performed to the acquisited data after then, also it will be lose the data at several channel. Therefore it is that the system uses efficiently the DSP and FPGA devices for reducing the data lose, it design to process a part of the signal data to FPGA from DSP in order to minimize the process time, and a process to parallel process system, as a result of design system it propose to method of faster process and more efficient data acquisition system by using DSP and FPGA than signal DSP system.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.7
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• pp.1147-1156
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• 2001

In this paper, a new design architecture of radar signal processor in real time is proposed. It has been designed and implemented under the consideration to minimize the inter-processor communication overhead and to maintain the coherence in Doppler pulse domain and in range domain. Its structure can be easily reconfigured and reprogrammed in accordance with an addition of function algorithm or a modification of operational scenario. As we designed a task configuration for parallel processing from measures of computation time for function algorithms and transmission time for results by signal processing, data exchange between processors for performing of function algorithms could be fully removed. Morocco-2 board equipped ADSP-21060 processor of Analog Devices inc. and APEX-3.2 developed for SHARC DSP were used to construct the radar signal processor.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.