• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.4
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• pp.41-49
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• 2008

H.264/AVC supports variable block motion compensation, multiple reference images, 1/4-pixel motion vector accuracy, and in-loop deblocking filter, compared with the existing compression technologies. While these coding technologies are major functions of compression rate improvement, they lead to high complexity at the same time. For the H.264 video coding technology to be actually applied on low-end / low-bit rates terminals more extensively, it is essential to improve tile coding speed. Currently the deblocking filter that can improve the moving picture's subjective image quality to a certain degree is used on low-end terminals to a limited extent due to computational complexity. In this paper, a performance improvement method of the deblocking filter that efficiently reduces the blocking artifacts occurred during the compression of low-bit rates digital motion pictures is suggested. In the method proposed in this paper, the image's spatial correlational characteristics are extracted by using the variable block information of motion compensation; the filtering is divided into 4 modes according to the characteristics, and adaptive filtering is executed in the divided regions. The proposed deblocking method reduces the blocking artifacts, prevents excessive blurring effects, and improves the performance about $30{\sim}40%$ compared with the existing method.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.168-180
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• 2018

In order to achieve the high quality output voltage of single-phase voltage source inverters, in this paper an Adaptive Complementary Sliding Mode Control (ACSMC) is proposed. Firstly, the dynamics model of the single-phase inverter with lumped uncertainty including parameter variations and external disturbances is derived. Then, the conventional Sliding Mode Control (SMC) and Complementary Sliding Mode Control (CSMC) are introduced separately. However, when system parameters vary or external disturbance occurs, the controlling performance such as tracking error, response speed et al. always could not satisfy the requirements based on the SMC and CSMC methods. Consequently, an ACSMC is developed. The ACSMC is composed of a CSMC term, a compensating control term and a filter parameters estimator. The compensating control term is applied to compensate for the system uncertainties, the filter parameters estimator is used for on-line LC parameter estimation by the proposed adaptive law. The adaptive law is derived using the Lyapunov theorem to guarantee the closed-loop stability. In order to decrease the control system cost, an inductor current estimator is developed. Finally, the effectiveness of the proposed controller is validated through Matlab/Simulink and experiments on a prototype single-phase inverter test bed with a TMS320LF28335 DSP. The simulation and experimental results show that compared to the conventional SMC and CSMC, the proposed ACSMC control strategy achieves more excellent performance such as fast transient response, small steady-state error, and low total harmonic distortion no matter under load step change, nonlinear load with inductor parameter variation or external disturbance.

• Journal of Korea Multimedia Society
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• v.21 no.5
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• pp.545-557
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• 2018

The Global Positioning System (GPS) has become popular and widely used in many fields from military to civilian applications. However, GPS signals are suffered from interference due to its weak signal over wireless channel. There are many types of interference, such as jamming, blocking multipath, and spoofing, which can mislead the operation of GPS receiver. In this paper, vector-based tracking loop model with integrity check is proposed to detect and mitigate the harmful effect of interference on GPS receiver operation. The suggested methods are implemented in the tracking loop of GPS receiver. As a first method, integrity check with carrier-to-noise ratio (C/No) monitoring technique is applied to detect the presence of interference and prevent contaminated channels out of tracking channels to calculate position. As a second method, a vector-based tracking loop using Extended Kalman Filter with adaptive noise covariance according to C/No monitoring results. The proposed methods have been implemented on simulated dataset. The results demonstrates that the suggested methods significantly mitigate interference of Additive White Gaussian Noise (AWGN) and improve position calculation by 44%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.37-44
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• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.543-545
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• 2017

This paper describes the SAO hardware architecture design for high performance in-loop filters. SAO is an inner module of in-loop filter, which compensates for information loss caused by block-based image compression and quantization. However, HEVC's SAO requires a high computation time because it performs pixel-unit operations. Therefore, the SAO hardware architecture proposed in this paper is based on a $4{\times}4$ block operation and a 2-stage pipeline structure for high-speed operation. The information generation and offset computation structure for SAO computation is designed in a parallel structure to minimize computation time. The proposed hardware architecture was designed with Verilog HDL and synthesized with TSMC chip process 130nm and 65nm cell library. The proposed hardware design achieved a maximum frequency of 476MHz yielding 163k gates and 312.5MHz yielding 193.6k gates on the 130nm and 65nm processes respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.1
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• pp.169-177
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• 2015

This paper proposes a hardware architecture for an efficient SAO(Sample Adaptive Offset) with low area for HEVC(High Efficiency Video Coding) encoder. SAO is a newly adopted technique in HEVC as part of the in-loop filter. SAO reduces mean sample distortion by adding offsets to reconstructed samples. The existing SAO requires a great deal of computational and processing time for UHD(Ultra High Definition) video due to sample by sample processing. To reduce SAO processing time, the proposed SAO hardware architecture processes four samples simultaneously, and is implemented with a 2-step pipelined architecture. In addition, to reduce hardware area, it has a single architecture for both luma and chroma components and also uses optimized and common operators. The proposed SAO hardware architecture is designed using Verilog HDL(Hardware Description Language), and has a total of 190k gates in TSMC $0.13{\mu}m$ CMOS standard cell library. At 200MHz, it can support 4K UHD video encoding at 60fps in real time, but operates at a maximum of 250MHz.

• ETRI Journal
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• v.33 no.2
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• pp.145-154
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• 2011

We present a novel video codec for supporting entertainment-quality video. It has new coding tools such as an intra prediction with offset, integer sine transform, and enhanced block-based adaptive loop filter. These tools are used adaptively in the processing of intra prediction, transform, and loop filtering. In our experiments, the proposed codec achieved an average reduction of 13.35% in BD-rate relative to H.264/AVC for 720p sequences.

• Advances in aircraft and spacecraft science
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• v.7 no.1
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• pp.1-17
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• 2020

In this paper, a new model-based Fault Detection and Diagnosis (FDD) method for an agile supersonic flight vehicle is presented. A nonlinear model, controlled by a classical closed loop controller and proportional navigation guidance in interception scenario, describes the behavior of the vehicle. The proposed FDD method employs the Inertial Navigation System (INS) data and nonlinear dynamic model of the vehicle to inform fins damage to the controller before leading to an undesired performance or mission failure. Broken, burnt, unactuated or not opened control surfaces cause a drastic change in aerodynamic coefficients and consequently in the dynamic model. Therefore, in addition to the changes in the control forces and moments, system dynamics will change too, leading to the failure detection process being encountered with difficulty. To this purpose, an equivalent aerodynamic model is proposed to express the dynamics of the vehicle, and the health of each fin is monitored by the value of a parameter which is estimated using an adaptive robust filter. The proposed method detects and isolates fins damages in a few seconds with good accuracy.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.12
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• pp.57-63
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• 2002

In this paper, the feedforward control with least mean square (LMS) adaptive algorithm is proposed and examined to reduce rotating error by runout of an active magnetic bearing system. Using eddy-current type gap sensor fur control, the electrical runout caused by non-uniform material properties of sensor target produces rotational error amplified in feedback control loop, so this runout should be eliminated to increase rotating accuracy. The adaptive feedforward controller is designed and examined its tracking and stability performances numerically with established frequency response function. The tested grinding spindle system is manufactured with a 5.5 ㎾ internal motor and 5-axis active magnetic bearing system including 5 eddy current gap sensors which have approximately 15 ~ 30 ${\mu}{\textrm}{m}$ of electrical runout. According to the experimental analysis, the error signal in radial bearings is reduced to less than 5 ${\mu}{\textrm}{m}$ when it is rotating up to 50,000 rpm due to applying the feedforward control for first order harmonic frequency, and vibration of the spindle base is also reduced about same frequency.

• Journal of Korea Society of Digital Industry and Information Management
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• v.10 no.3
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• pp.119-125
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• 2014

Echo cancellation is required for a dual-duplex high speed communication such as digital subscriber line(DSL), in order to allow each individual loop to operate in a full duplex fashion. Echo cancellation was one of the most difficult aspects of DSL design, requiring high linearity and total echo return loss in excess of 70 dB. For a long and rapidly changing echo response, if the echo is cancelled by an adaptive echo canceller, the echo canceller needs more taps and its performance is decreased. But if the response is divided into several responses, which response is estimated by a adaptive digital filter and combined, the computation complexities are decreased and the performance is increased. Therefore, the adaptive multi-stage echo canceller is proposed to decrease the computation complexity and increase the performance of echo return loss, in which the echo canceller is composed of several stage echo canceller estimating each divided echo response. Through computer simulations, this multi-stage echo canceller is verified to have merits for high speed communications such as DSL application.