• ETRI Journal
• /
• v.32 no.1
• /
• pp.84-92
• /
• 2010

This paper proposes the semaphore authority management (SAM) controller to optimize the dual-port SDRAM (DPSDRAM) in the mobile multimedia systems. Recently, the DPSDRAM with a shared bank enabling the exchange of data between two processors at high speed has been developed for mobile multimedia systems based on dual-processors. However, the latency of DPSDRAM caused by the semaphore for preventing the access contention at the shared bank slows down the data transfer rate and reduces the memory bandwidth. The methodology of SAM increases the data transfer rate by minimizing the semaphore latency. The SAM prevents the latency of reading the semaphore register of DPSDRAM, and reduces the latency of waiting for the authority of the shared bank to be changed. It also reduces the number of authority requests and the number of times authority changes. The experimental results using a 1 Gb DPSDRAM (OneDRAM) with the SAM controllers at 66 MHz show 1.6 times improvement of the data transfer rate between two processors compared with the traditional controller. In addition, the SAM shows bandwidth enhancement of up to 38% for port A and 31% for port B compared with the traditional controller.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.16 no.1
• /
• pp.233-238
• /
• 2016

Recently, the multi-core processor architecture is widely adopted in the embedded processors for enhancing its performance. Multi-core processors are classified either as symmetric or asymmetric. Asymmetric multicore processors are known to score higher performance and more efficient than symmetric multi-core processors. In order to study the performance enhancement of asymmetric multi-core embedded processors over the symmetric ones, the trace-driven simulation has been executed for various asymmetric embedded dual-core, quad-core, octa-core and hexadeca-core processors and compared with the symmetric ones of similar hardware budget using MiBench benchmarks as input.

• The KIPS Transactions:PartA
• /
• v.8A no.4
• /
• pp.419-428
• /
• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.6
• /
• pp.703-709
• /
• 2014

In the AMP(Asymmetric Multiprocessing) based dual core using core-specific operating system in a single processor system, shared memory method is used to send data between processors in dual core. To used shared memory in different operating systems, there is a problem of needing to solving the issue of message communication and synchronization between the two operations systems. In this paper, separate memory controller was used for data sharing between different processor cores in dual core environment. This controller can designate two slave ports to allow simultaneous access from two processors, and in the case of process data simultaneously by two processors, priority order of slave ports is determined through memory mediator. When sending data from A to B processor, SRAM area was logically separated into 8 pages. It allowed using memory area from multiple processes with the size of 4KByte per page, and control register with the size of 4Byte was used to discern the usability of current page.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.21 no.8
• /
• pp.1989-2002
• /
• 1996

In this paper, we describe several warm standby fault-tolerant models and their operation methods applicable to telephone switching control systems which have dual module structure and need high availability. Unavailabilities of the system implemented by four different methods for each model are computed by using the Markov state model, and then are compared for system performance evaluation. As the results ofsimulations, the warm standby model with triple processors is best in the aspect of data loss, while in most cases the warm standby model with doble processors based on no standby check method provides the highest system avaiability. Periodic changeover increases the system unavailability, but the preriodic standby check on standby module decreases the system unavailability of warm standby model with a single processor and with double processors. On the other hands, the variationas of warm standby model with a single processor and with double processors. On the other hand, the variations of data recovery time and personnel recovery rate have little effect on the system unavailtability.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2011.04a
• /
• pp.46-49
• /
• 2011

This paper is to implement MoIP platform to send and receive video and audio at the same time by using high-performance Dual Core Processor. Even if Wall-Pad key component of a home network system is released by using embedded processors, it's lacking of performance in terms of multimedia processing and feature of video telephony through which video and voice are exchanged simultaneously. The main reason could be that embedded processors currently being used do not provide enough performance to support both MoIP call features and various home network features simultaneously. In order to solve these problems, Dual processor could be used, but in the other hands it brings another disadvantage of high cost. Therefore, this study is to solve the home automation features and video telephony features by using Dual Core Processor based on ARM 11 Processor and implement the MoIP Wall-Pad which can reduce the board design costs and component costs, and improve performance. The platform designed and implemented in this paper verified performance of MoIP to exchange the video and voice at the same time under the situation of Ethernet network.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.8 no.7
• /
• pp.1553-1557
• /
• 2004

A real-time processing system for embedded hardware genetic algorithm is suggested. In order to operate basic module of genetic algorithm in parallel, such as selection, crossover, mutation and evaluation, dual processors based architecture is implemented. The system consists of two Xscale processors and two FPGA with evolvable hardware, which enables to process genetic algorithm efficiently by distributing the computational load of hardware genetic algorithm to each processors equally. The hardware genetic algorithm runs on Linux OS and the resulted chromosome is executed on evolvable hardware in FPGA. Furthermore, the suggested architecture can be extended easily for a couple of connected processors in serial, making it accelerate to compute a real-time hardware genetic algorithm. To investigate the effect of proposed approach, performance comparisons is experimented for an typical computation of genetic algorithm.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 2006.07a
• /
• pp.571-571
• /
• 2006

• Proceedings of the IEEK Conference
• /
• 2005.11a
• /
• pp.829-832
• /
• 2005

This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

• 제어로봇시스템학회:학술대회논문집
• /
• 2003.10a
• /
• pp.2540-2545
• /
• 2003

We propose a new technique to the design and real-time implementation of an adaptive controller for robotic manipulator based on digital signal processors in this paper. The Texas Instruments DSPs(TMS320C80) chips are used in implementing real-time adaptive control algorithms to provide enhanced motion control performance for dual-arm robotic manipulators. In the proposed scheme, adaptation laws are derived from model reference adaptive control principle based on the improved direct Lyapunov method. The proposed adaptive controller consists of an adaptive feed-forward and feedback controller and time-varying auxiliary controller elements. The proposed control scheme is simple in structure, fast in computation, and suitable for real-time control. Moreover, this scheme does not require any accurate dynamic modeling, nor values of manipulator parameters and payload. Performance of the proposed adaptive controller is illustrated by simulation and experimental results for a dual arm robot consisting of two 4-d.o.f. robots at the joint space and cartesian space.