• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.26 no.2
• /
• pp.135-147
• /
• 2015

With the miniaturization and digitalization of electronics industry, demand for Multi-Layer Ceramic Capacitor(MLCC) has increased steadily because of its various applications such as DC Blocking, Decoupling and Filtering etc. The modeling techniques of MLCC has been studied for a long time but most of these modeling method can only be applied after measurement and this has some losses of material, time in both production stage and measurement stage. This paper proposes the modeling method which can predict the frequency characteristics of MLCC from structure data and material data in design stage. The impedance of N-Layer Capacitor can be expressed in differential mathematical form based on coupled transmission line equations. By using this formula, we can predict the impedance of MLCC. As a result, proposed modeling is correspond with simulation, and it takes much less time to obtain the result than the simulation.

• Journal of Electrical Engineering and Technology
• /
• v.10 no.4
• /
• pp.1621-1625
• /
• 2015

Power quality has always been a concern of power engineers. Certainly an argument can be successfully made that most parts of power engineering have the ultimate objective to improve power quality. AC motors were widely used in industrial and domestic applications. Generally, AC motors were of two types: Induction and Synchronous motors. In motor many parameters like different load cycling, switching, working in hot weather and unbalances creates harmonics which creates major reasons for temperature rise of the motors. Due to high peak value of voltage, harmonics can weaken insulation in cables, windings and capacitors and different electronic components. Higher value of harmonics increase the motor current and decrease the power factor which will reduce the life time of the motor and increase the overall rating of all electrical equipments. Harmonics reduction of all the motors in India will save more power. Coating of windings of the motor with nano fillers will reduce the amount of harmonics in the motor. Based on the previous project works, actions were taken to use the enamel filled with various nano fillers for the coating of the windings of the different AC motors. Ball mill method was used to convert the micro particles of Al₂O₃, SiO₂, TiO₂, ZrO₂ and ZnO into nano particles. SEM, TEM and XRD were used to augment the particle size of the powder. The synthesized nano powders were mixed with the enamel by using ultrasonic vibrator. Then the enamel mixed with the nano fillers was coated to the windings of the several AC motors. Harmonics were measured in terms of various indices like THD, VHD, CHD and DIN by using Harmonic analyzer. There are many other measures and indices to describe power quality, but none is applicable in all cases and in many instances, these indices may hide more than they show. Sometimes power quality indices were used as a basis of comparison and standardization. The efficiency of the motors was increased by 5 – 10 %. The thermal withstanding capacity of the motor was increased by 5º to 15º C. The harmonics of the motors were reduced by 10 – 50%.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.17 no.7
• /
• pp.42-48
• /
• 2016

In this paper, a high-precision peak detector circuit that detects the output voltage information of a fly-back converter is proposed. The proposed design consists of basic analog elements with only one operational amplifier and three transistors. Because of its simple structure, the proposed circuit can minimize the delay time of the detection process, which has a strong impact on the precision of the regulation aspect of the fly-back converter. Furthermore, by using an amplifier and several transistors, the proposed detector can be fully integrated on-chip, instead of using discrete circuit elements, such as capacitors and diodes, as in conventional designs, which reduces the production cost of the fly-back converter module. In order to verify the performance of the proposed scheme, the peak detector was simulated and implemented by using a 0.35 m MagnaChip process. The gained results from the simulation with a sinusoidal stimulus signal show a very small detection error in the range of 0.3~3.1%, which is much lower than other reported detecting circuits. The measured results from the fabricated chip confirm the simulation results. As a result, the proposed peak detector is recommended for designs of high-performance fly-back converters in order to improve the poor regulation aspect seen in conventional designs.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.1
• /
• pp.7-15
• /
• 2004

The ferroelectric SBT thin films as a material of capacitors for non-volatile FRAMs have some problems that its remanent polarization value is relatively low and the crystallization temperature is quite high abovc 80$0^{\circ}C$. Therefore, in this paper, SBTN solution with S $r_{0.9}$B $i_{2.1}$T $a_{1.8}$N $b_{0.2}$$O_{9}$ composition was synthesized by sol-gel method. Sr(O $C_2$ $H_{5}$)$_2$, Bi(TMHD)$_3$, Ta(O $C_2$ $H_{5}$)$_{5}$and Nb(O $C_2$ $H_{5}$)$_{5}$ were used as precursors, which were dissolved in 2-methoxyethanol. SBTN thin films with 200 nm thickness were deposited on Pt/Ti $O_2$/ $SiO_2$/Si substrates by spin-coating. UV-irradiation in a power of 200 W for 10 min and rapid thermal annealing in a 5-Torr-oxygen ambient at 76$0^{\circ}C$ for 60 sec were used to promote crystallization. The films were well crystallized and fine-grained after annealing at $650^{\circ}C$ in oxygen ambient. The electrical characteristics of 2Pr=11.94 $\mu$C/$\textrm{cm}^2$, Ps＋/Pr＋=0.54 at the applied voltage of 5 V were obtained for a 200-nm-thick SBTN films. This results show that 2Pr values of the UV irradiated and rapid thermal annealed SBTN thin films at the applied voltage of 5 V were about 57% higher than those of no additional processed SBTN thin films. thin films.lms.s.s.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.5
• /
• pp.27-37
• /
• 1999

A CMOS ReadOut Integrated Circuit (ROlC) for InfraRed Focal Plane Array (IRFPA) detector is presented, which is a key component in uncooled thermal imaging systems. The ROIC reads out signals from $64\times64$ Barium Strontium Titanate (BST) infrared detector array, then outputs pixel signals sequentially after amplifying and noise filtering. Various design requirements and constraints have been considered including impedance matching, low noise, low power dissipation and small detector pitch. For impedance matching between detector and pre~amplifier, a new circuit based on MOS diode structure is devised, which can be easily implemented using standard CMOS process. Also, tunable low pass filter with single~pole is used to suppress high frequency noise. In additions, a clamping circuit is adopted to enhance the signal~to-noise ratio of the readout output signals. The $64\times64$ IRFPA ROIC is designed using $0.65-\mu\textrm{m}$ 2P3M (double poly, tripple metal) N~Well CMOS process. The core part of the chip contains 62,000 devices including transistors, capacitors and resistors on an area of about $6.3-mm\times6.7-mm$.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.8
• /
• pp.107-114
• /
• 2017

In this paper, a novel power factor compensation system based on voltage-controlled method is proposed for 3-phase 4-wire power system. The proposed voltage-controlled power factor compensation system generates a reactive power required for compensation by applying a variable output voltage by a slidac to a capacitor. In conventional power factor compensation system using the capacitor bank method, the power factor compensation error occurs depending on the load condition due to the limited capacity of the capacitors. However, the proposed system compensates the power factor up to 100% without error. In this paper, we have developed a voltage-controlled power factor compensation system and a control algorithm for 3-phase 4-wire power system, and verify its performance through simulation and experiments. If the proposed power factor compensation system is applied to an industrial field, a power factor compensation performance can be maximized. As a result, it is possible to reduce of electricity prices, reduce of line loss, increase of load capacity, ensure the transmission margin capacity, and reduce the amount of power generation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.28 no.1
• /
• pp.69-75
• /
• 2017

In this paper, slit ground resonator with slit and capacitor is proposed for practical use of magnetic resonant wireless power transfer(MR-WPT). And this paper presents the performance comparison of conventional loop resonator as Rx resonator to slit ground resonator. The proposed silt ground resonator with 31 cm width, 20.5 cm length, $35{\mu}m$ thickness is designed the crossing slit 1 cm width with only opened edge. And an external capacitors were connected at the opened edge of slit ground resonator for resonating at 6.78 MHz. The transfer efficiencies of MR-WPT were measured at open and short mode, and then the highest transfer efficiencies of MR-WPT according to the Rx resonators were plotted. In result, the transfer efficiency of MR-WPT with loop resonator was the highest. However, when the ground was inserted in receiver part at the bottom of laptop model, the transfer efficiency was closed 0 %. The transfer efficiency recovered the transfer efficiency of 67 % using slit ground resonator. The magnetic field was penetrated through the slit and proposed slit ground resonator works as resonator in MR-WPT.

• Journal of the Microelectronics and Packaging Society
• /
• v.14 no.2 s.43
• /
• pp.41-47
• /
• 2007

Today lots of investigations on Embedded Passive Technology using materials and chip components have been carried out. We fabricated diplexers with 1005 sized-passives, which were made by burying chips in PCB substrate and surface mounting chip on PCB. 6 passive chips (inductors and capacitors) were used for the frequency divisions of $880\;MHz{\sim}960\;MHz(GSM)$ and $1.71\;GHz{\sim}1.88\;GHz(DCS)$. Two types of diplxer were characterized with Network analyzer. The chip buried diplexer showed extra 5db loss and a little deviation of 0.6GHz at aimed frequency areas, whereas the chip mounted diplexer showed man. 0.86dB loss within GSM field and max. 0.68dB within DCS field respectively. But few degradations were observed after $260^{\circ}C$ for 80min baking and $280^{\circ}C$ for 10sec solder floating.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.12
• /
• pp.56-63
• /
• 1994

The effects of sulfur treatments on the barrier heithts of Schottky contacts and the interface-state density of metal-insulator-semiconductor (MIS) capacitors on InP have been investigated. Schottky contacts were formed by the evaporation of Al, Au, and Pt on n-InP substrate before and after (NH$_{4}$)$_{2}$S$_{x}$ treatments, respectively. The barrier height of InP Schottky contacts was measured by their current-voltage (I-V) and capacitance-voltage (C_V) characteristics. We observed that the barrier heights of Schottky contacks on bare InP were 0.35~0.45 eV nearly independent of the metal work function, which is known to be due to the surface Fermi level pinning. In the case of sulfur-treated Au/InP ar Pt/InP Schottky diodes, However, the barrier heights were not only increased above 0.7 eV but also highly dependent on the metal work function. We have also investigated effects of (NH$_{4}$)$_{2}$S$_{x}$ treatments on the distribution of interface states in Si$_{3}$N$_{4}$InP MIS diodes where Si$_{3}$N$_{4}$ was provided by plasma enhanced chemical vapor deposition (PECVD). The typical value of interface-state density extracted feom 1 MHz C-V curve of sulfur-treated SiN$_{x}$/InP MIS diodes was found to be the order of 5${\times}10^{10}cm^{2}eV^{1}$. This value is much lower than that of MiS diodes made on bare InP surface. It is certain, therefore, that the (NH$_{4}$)$_{2}$S$_{x}$ treatment is a very powerful tool to enhance the barrier heights of Au/n-InP and Pt/n-InP Schottky contacts and to reduce the density of interface states in SiN$_{x}$/InP MIS diode.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.37 no.11
• /
• pp.18-24
• /
• 2000

(Ba,Sr)$TiO_3$ thin films have attracted great interest as new dielectric materials of capacitors for ultra-large-scale integrated dynamic random access memories (ULSI-DRAMs) such as 1 Gbit or 4 Gbit. In this study, inductively coupled $BCl_3/Cl_2/Ar$ plasmas was used to etch (Ba,Sr)$TiO_3$ thin films. RF power/dc bias voltage=600 W/-250 V and chamber pressure was 10 mTorr. The $Cl_2/(Cl_2+Ar)$ was fixed at 0.2 the (Ba,Sr)$TiO_3$ thin films were etched adding $BCl_3$. The highest (Ba,Sr)$TiO_3$ etch rate is $480{\AA}/min$ at 10 % $BCl_3$ to $Cl_2/Ar$. The change of Cl, B radical density measured by optical emission spectroscopy(OES) as a function of $BCl_3$ percentage in $Cl_2/Ar$. The highest Cl radical density was shown at the addition of 10% $BCl_3$ to $Cl_2/Ar$. To study on the surface reaction of (Ba, Sr)$TiO_3$ thin films was investigated by XPS analysis. Ion bombardment etching is necessary to break Ba-O bond and to remove $BaCl_2$. There is a little chemical reaction between Sr and Cl, but Sr is removed by physical sputtering. There is a chemical reaction between Ti and Cl, and $TiCl_4$ is removed with ease. The cross-sectional of (Ba,Sr)$TiO_3$ thin film was investigated by scanning electron microscopy (SEM), the etch slope is about 65~70$^{\circ}$.