• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1527-1539
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• 2015

In this paper the hardware implementation of the direct torque control based on the fuzzy logic technique of induction motor on the Field-Programmable Gate Array (FPGA) is presented. Due to its complexity, the fuzzy logic technique implemented on a digital system like the DSP (Digital Signal Processor) and microcontroller is characterized by a calculating delay. This delay is due to the processing speed which depends on the system complexity. The limitation of these solutions is inevitable. To solve this problem, an alternative digital solution is used, based on the FPGA, which is characterized by a fast processing speed, to take the advantage of the performances of the fuzzy logic technique in spite of its complex computation. The Conventional Direct Torque Control (CDTC) of the induction machine faces problems, like the high stator flux, electromagnetic torque ripples, and stator current distortions. To overcome the CDTC problems many methods are used such as the space vector modulation which is sensitive to the parameters variations of the machine, the increase in the switches inverter number which increases the cost of the inverter, and the artificial intelligence. In this paper an intelligent technique based on the fuzzy logic is used because it is allows controlling the systems without knowing the mathematical model. Also, we use a new method based on the Xilinx system generator for the hardware implementation of Direct Torque Fuzzy Control (DTFC) on the FPGA. The simulation results of the DTFC are compared to those of the CDTC. The comparison results illustrate the reduction in the torque and stator flux ripples of the DTFC and show the Xilinx Virtex V FPGA performances in terms of execution time.

• Convergence Security Journal
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• v.12 no.4
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• pp.17-23
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• 2012

Recently, the research for cryptographic algorithm, in particular, a stream cipher has been actively conducted for wireless devices as growing use of wireless devices such as smartphone and tablet. LFSR based random number generator is widely used in stream cipher since it has simple architecture and it operates very fast. However, the conventional multi-LFSR RNG (random number generator) suffers from its hardware complexity as well as very closed correlation between the numbers generated. A leap-ahead LFSR was presented to solve these problems. However, it has another disadvantage that the maximum period of the generated random numbers are significantly decreased according to the relationship between the number of the stages of the LFSR and the number of the output bits of the RNG. This paper presents new leap-ahead LFSR architecture to prevent this decrease in the maximum period by applying segmentation technique to the conventional leap-ahead LFSR. The proposed architecture is implemented using VHDL and it is simulated in FPGA using Xilinx ISE 10.1, with a device Virtex 4, XC4VLX15. From the simulation results, the proposed architecture has only 20% hardware complexity but it can increases the maximum period of the generated random numbers by 40% compared to the conventional Leap-ahead archtecture.

• Journal of Computing Science and Engineering
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• v.12 no.1
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• pp.24-35
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• 2018

Deep convolutional neural network (DCNN) is an advanced technology in image recognition. Because of extreme computing resource requirements, DCNN implementation with software alone cannot achieve real-time requirement. Therefore, the need to implement DCNN accelerator hardware is increasing. In this paper, we present a field programmable gate array (FPGA)-based hardware accelerator design of DCNN targeting handwritten Hangul character recognition application. Also, we present design optimization techniques in SDAccel environments for searching the optimal FPGA design space. The techniques we used include memory access optimization and computing unit parallelism, and data conversion. We achieved about 11.19 ms recognition time per character with Xilinx FPGA accelerator. Our design optimization was performed with Xilinx HLS and SDAccel environment targeting Kintex XCKU115 FPGA from Xilinx. Our design outperforms CPU in terms of energy efficiency (the number of samples per unit energy) by 5.88 times, and GPGPU in terms of energy efficiency by 5 times. We expect the research results will be an alternative to GPGPU solution for real-time applications, especially in data centers or server farms where energy consumption is a critical problem.

• Journal of Advanced Navigation Technology
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• v.15 no.2
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• pp.298-306
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• 2011

In this paper, the RUNCODE encoder hardware IP was designed and implemented for symbol ID code length encoding, which is one of major modules of JBIG2 encoder for FAX. ImpulseC Codeveloper and Xilinx ISE/EDK program are used for the hardware generation and synthesis of VHDL code. The synthesized hardware was downloaded to Virtex-4 FX60 FPGA on ML410 development board. The synthesized hardware utilizes 13% of total slice of FPGA. Using Active-HDL tool, the hardware was verified showing normal operation. Compared with the software operating using Microblaze cpu on ML410 board, the synthesized hardware was better in operation time. The improvement ratio of operation time between the synthesized hardware and software showed about 40 times faster than software only operation. The synthesized H/W and S/W module cooperated to succeed in compressing the CCITT standard document.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.5
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• pp.452-459
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• 2020

The electric actuator receives the user's command input signal (open/closed/stop), checks the status of various sensors (valve position, rotational force, motor status, etc.)in the actuator, and controls the motor forward/reverse to open and close the valve. It is a device that outputs the current state of an actuator (valve) and is used in various fields such as dams, power plants, water and sewage facilities, and oil pipeline facilities. If an electric actuator is installed in a power plant and a problem occurs during operation, it can cause a large economic loss, so system reliability is vert important. In this study, in order to increase the safety of the electric actuator, the development of an electric actuator control device capable of setting the ON/OFF time in hardware was conducted to solve the reliability problem that may occur in software. In addition, the electric actuator control device development environment was developed using Xilinx's Spartan7 FPGA and Altium tool.

• Journal of IKEEE
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• v.27 no.4
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• pp.494-500
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• 2023

Image processing is currently used in various fields. Among them, autonomous vehicles, medical image processing, and robot control require fast image processing response speeds. To fulfill this requirement, hardware design for real-time processing is being actively researched. In addition to the size of the input image, the hardware processing speed is affected by the size of the inactive video periods that separate lines and frames in the image. In this paper, we design three different scaler structures based on the type of line memories, which is closely related to the inactive video periods. The structures are designed in hardware using the Verilog standard language, and synthesized into logic circuits in a field programmable gate array environment using Xilinx Vivado 2023.1. The synthesized results are used for frame rate analysis while comparing standard image sizes that can be processed in real time.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.3
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• pp.57-62
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• 2022

Recently, the tracking radar continues research to develop a new operation algorithm that can acquire and track a target in various environments. In general, modeling similar to the real target and environment is used to develop a new operation algorithm, but there is a limit to modeling the real environment. In this paper, a RAW data storage device was developed to efficiently develop a new operation algorithm required for the tracking radar using millimeter wave to acquire and track the target. The RAW data storage equipment is designed so that the signal processing device of the tracking radar using millimeter wave can save the RAW data output from 8 channels to OOOMSPS. RAW data storage equipment consists of data acquisition equipment and data storage equipment. The data acquisition equipment was implemented using a commercial Xilinx KCU 105 Evaluation KIT capable of high-speed data communication interface, and the data storage equipment was implemented by applying a computer compatible with the commercial Xilinx KCU 105 Evaluation KIT. In this paper, the performance of the implemented RAW data storage equipment was verified through repeated interlocking tests with the signal processing device of the millimeter wave tracking radar.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.109-116
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• 2003

In this paper. we Propose an UXGA class LCD controller for controlling the LCD panel. The proposed controller supports the full screen display using GCD between input and output resolutions. The proposed LCD controller includes the motion detector based on median filter which can detect the motion of input image for the enhancement of a image quality. Also, it divides the motion into 3 stages such as still, semi-moving and moving, and uses the different interpolation algorithms according to the degree of motion. In order to evaluate the performance of the proposed interpolation algorithm, we use PSNR method and compare the conventional algorithm by using computer simulation. For the proposed motion detection algorithm, we use a visual verification and the estimation of pixel changes. The proposed LCD controller has been designed and verified by VHDL. It has been synthesized using Xilinx VirtexE FPGA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.61-70
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• 2004

In this paper, we propose the color-temperature conversion system with compensated X-chromaticity coordinate. It uses a linear regression to improve the error of color-temperatue calculation in conventional systems. It also extend the color-temperature range from 1,667K to 25,000K to Provide a wider color-temperature range. We show the effectiveness of the proposed method by comparing the performance of the proposed method with those of the Robertson's and the existing methods. The proposed method is experimetally verified by displaying the results on a TV system through the Xilinx FPGA XCV2000E-BG560.

• Journal of IKEEE
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• v.13 no.4
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• pp.57-62
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• 2009

In this paper, to implement PCS (Physical Coding Sublayer) of 10GBASE-R type, we present 2 stage pipeline 64b/66b Encoder/Decoder which operates at 156.25MHz standard specification and designed to minimize clock latency as possible as we can. The proposed circuit was designed based on Verilog hardware description language and measured for functional verification on VertexII-1000fg456 chip of Xilinx Inc.. Total equivalent gate count is 47,303 and estimated power consumption is 351mW at Vcc 3.3V.