• Journal of Korea Society of Industrial Information Systems
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• v.22 no.4
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• pp.1-9
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• 2017

In this Paper, Double Encryption Technology Based on Phase-Shifting Digital Holography and Digital Watermarking is Proposed. For the Purpose, we First Set a Logo Image to be used for Digital Watermark and Design a Binary Phase Computer Generated Hologram for this Logo Image using an Iterative Algorithm. And Random Generated Binary Phase Mask to be set as a Watermark and Key Image is Obtained through XOR Operation between Binary Phase CGH and Random Binary Phase Mask. Object Image is Phase Modulated to be a Constant Amplitude and Multiplied with Binary Phase Mask to Generate Object Wave. This Object Wave can be said to be a First Encrypted Image Having a Pattern Similar to the Noise Including the Watermark Information. Finally, we Interfere the First Encrypted Image with Reference Wave using 2-step PSDH and get a Good Visible Interference Pattern to be Called Second Encrypted Image. The Decryption Process is Proceeded with Fresnel Transform and Inverse Process of First Encryption Process After Appropriate Arithmetic Operation with Two Encrypted Images. The Proposed Encryption and Decryption Process is Confirmed through the Computer Simulations.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.18 no.2
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• pp.3-10
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• 2008

The choice of basis for representation of element in $GF(2^m)$ affects the efficiency of a multiplier. Among them, a multiplier using redundant representation efficiently supports trade-off between the area complexity and the time complexity since it can quickly carry out modular reduction. So time of a previous multiplier using redundant representation is faster than time of multiplier using others basis. But, the weakness of one has a upper space complexity compared to multiplier using others basis. In this paper, we propose a new efficient multiplier with consideration that polynomial exponentiation operations are frequently used in cryptographic hardwares. The proposed multiplier is suitable fer left-to-right exponentiation environment and provides efficiency between time and area complexity. And so, it has both time delay of $T_A+({\lceil}{\log}_2m{\rceil})T_x$ and area complexity of (2m-1)(m+s). As a result, the proposed multiplier reduces $2(ms+s^2)$ compared to the previous multiplier using equally-spaced polynomials in area complexity. In addition, it reduces $T_A+({\lceil}{\log}_2m+s{\rceil})T_x$ to $T_A+({\lceil}{\log}_2m{\rceil})T_x$ in the time complexity.($T_A$:Time delay of one AND gate, $T_x$:Time delay of one XOR gate, m:Degree of equally spaced irreducible polynomial, s:spacing factor)

• The Journal of the Korea Contents Association
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• v.21 no.3
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• pp.616-625
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• 2021

Deep neural networks are an approximation method that approximates an arbitrary function to a linear model and then repeats additional approximation using a nonlinear active function. In this process, the method of evaluating the performance of approximation uses the loss function. Existing in-depth learning methods implement approximation that takes into account loss functions in the linear approximation process, but non-linear approximation phases that use active functions use non-linear transformation that is not related to reduction of loss functions of loss. This study proposes parametric activation functions that introduce scale parameters that can change the scale of activation functions and location parameters that can change the location of activation functions. By introducing parametric activation functions based on scale and location parameters, the performance of nonlinear approximation using activation functions can be improved. The scale and location parameters in each hidden layer can improve the performance of the deep neural network by determining parameters that minimize the loss function value through the learning process using the primary differential coefficient of the loss function for the parameters in the backpropagation. Through MNIST classification problems and XOR problems, parametric activation functions have been found to have superior performance over existing activation functions.

• KIPS Transactions on Computer and Communication Systems
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• v.12 no.9
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• pp.283-290
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• 2023

With the recent steady development of IoT technology, it is widely used in medical systems and smart TV watches. 66% of software development is developed through language C, which is vulnerable to memory attacks, and acts as a threat to IoT devices using language C. A stack-smashing overflow attack inserts a value larger than the user-defined buffer size, overwriting the area where the return address is stored, preventing the program from operating normally. IoT devices with low memory capacity are vulnerable to stack smashing overflow attacks. In addition, if the existing vaccine program is applied as it is, the IoT device will not operate normally. In order to defend against stack smashing overflow attacks on IoT devices, we used canaries among several detection methods to set conditions with random values, checksum, and DSLR (random storage locations), respectively. Two canaries were placed within the buffer, one in front of the return address, which is the end of the buffer, and the other was stored in a random location in-buffer. This makes it difficult for an attacker to guess the location of a canary stored in a fixed location by storing the canary in a random location because it is easy for an attacker to predict its location. After executing the detection program, after a stack smashing overflow attack occurs, if each condition is satisfied, the program is terminated. The set conditions were combined to create a number of eight cases and tested. Through this, it was found that it is more efficient to use a detection method using DSLR than a detection method using multiple conditions for IoT devices.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.3
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• pp.707-714
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• 2010

Since an LFSR(linear feedback shift register) as a pattern generator has solely linear dependency in itself, it generates sequences by moving the bit positions for pattern generation. So the correlation between the generated patterns is high and thus reduces the possibility of fault detection. To overcome these problems many researchers studied to have goodness of randomness between the output test patterns. In this paper, we propose the new and effective method to construct phase shifter as PRPG(pseudo random pattern generator).

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.7
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• pp.3444-3449
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• 2013

The control module controlling points has become high-tech. but the introduction of relevant company's inspection intervals and methods, and the adoption of the way which is used in relay interlock system became the cause of a failure by excessive and incorrect maintenance. The Human error in failure recovery process can cause vital accidents including train derailment, the points monitoring system could prevent this problem by monitoring points' operation condition in real time. After conducting the changed inspection intervals that applied the results of the criticality of each failure type, MTBF, MTTR, availability, maintainer's opinion, the work became simplified, and, the failure did not occur for 4 consecutive years in contrast to the previous annual average of 11 failures.

• ETRI Journal
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• v.35 no.3
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• pp.448-458
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• 2013

This paper presents a generalized post-processing technique for enhancing the pseudorandomness of digital chaotic oscillators through a nonlinear XOR-based operation with rotation and feedback. The technique allows full utilization of the chaotic output as pseudorandom number generators and improves throughput without a significant area penalty. Digital design of a third-order chaotic system with maximum function nonlinearity is presented with verified chaotic dynamics. The proposed post-processing technique eliminates statistical degradation in all output bits, thus maximizing throughput compared to other processing techniques. Furthermore, the technique is applied to several fully digital chaotic oscillators with performance surpassing previously reported systems in the literature. The enhancement in the randomness is further examined in a simple image encryption application resulting in a better security performance. The system is verified through experiment on a Xilinx Virtex 4 FPGA with throughput up to 15.44 Gbit/s and logic utilization less than 0.84% for 32-bit implementations.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.3 s.309
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• pp.10-19
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• 2006

In this paper, we propose 128-bit chaotic block encryption scheme using a PLCM(Piecewise Linear Chaotic Map) having a good dynamical property. The proposed scheme has a block size of 12n-bit and a key size of 125-bit. The encrypted code is generated from the output of PLCM. We show the proposed scheme is very secure against statistical attacks and have very good avalanche effect and randomness properties.

• International Journal of Contents
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• v.10 no.1
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• pp.62-67
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• 2014

Usually, cloud storage systems are developed based on DFS (Distributed File System) for scalability and reliability reasons. DFSs are designed to improve throughput than IO response time, and therefore, they are appropriate for batch processing jobs. Recently, cloud storage systems have been used for update intensive applications such as OLTP and so on. However, in DFSs, in-place update operations are not carefully considered. Therefore, when updates are frequent, I/O performance of DFSs are degraded significantly. DFSs with RAID techniques have been proposed to improve their performance and reliability. Their performance degradation caused by frequent update operations can be more significant. In this paper, we propose an in-place update method for DFS RAID exploiting a differential logging technique. The proposed method reduces the I/O costs, network traffic and XOR operation costs for RAID. We demonstrate the efficiency of our proposed in-place update method through various experiments.

• Journal of Electrical Engineering and Technology
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• v.3 no.1
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• pp.43-51
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• 2008

Evolutionary Algorithms (EAs) cover all the applications involving the use of Evolutionary Computation in electronic system design. It is largely applied to complex optimization problems. EAs introduce a new idea for automatic design of electronic systems; instead of imagine model, ions, and conventional techniques, it uses search algorithm to design a circuit. In this paper, a method for automatic optimization of the digital circuit design method has been introduced. This method is based on randomized search techniques mimicking natural genetic evolution. The proposed method is an iterative procedure that consists of a constant-size population of individuals, each one encoding a possible solution in a given problem space. The structure of the circuit is encoded into a one-dimensional genotype as represented by a finite string of bits. A number of bit strings is used to represent the wires connection between the level and 7 types of possible logic gates; XOR, XNOR, NAND, NOR, AND, OR, NOT 1, and NOT 2. The structure of gates are arranged in an $m{\times}n$ matrix form in which m is the number of input variables.