• Title/Summary/Keyword: Worst case execution time(WCET)

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A Checkpointing Framework for Dependable Real-Time Systems (고신뢰 실시간 시스템을 위한 체크포인팅 프레임워크)

  • Lee, Hyo-Soon;Shin, Heonshik-Sin
    • Journal of KIISE:Computer Systems and Theory
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    • v.29 no.4
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    • pp.176-184
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    • 2002
  • We provide a checkpointing framework reflecting both the timeliness and the dependability in order to make checkpointing applicable to dependable real-time systems. The predictability of real-time tasks with checkpointing is guaranteed by the worst case execution time (WCET) based on the allocated number of checkpoints and the permissible number of failures. The permissible number of failures is derived from fault tolerance requirements, thus guaranteeing the dependability of tasks. Using the WCET and the permissible number of failures of tasks, we develop an algorithm that determines the minimum number of checkpoints allocated to each task in order to guarantee the schedulability of a task set. Since the framework is based on the amount of time redundancy caused by checkpointing, it can be extended to other time redundancy techniques.

Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches

  • Yan, Jun;Zhang, Wei
    • Journal of Computing Science and Engineering
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    • v.5 no.1
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    • pp.1-18
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    • 2011
  • As the first step toward real-time multi-core computing, this paper presents a novel approach to bounding the worst-case performance for threads running on multi-core processors with shared L2 instruction caches. The idea of our approach is to compute the worst-case instruction access interferences between different threads based on the program control flow information of each thread, which can be statically analyzed. Our experiments indicate that the proposed approach can reasonably estimate the worst-case shared L2 instruction cache misses by considering the inter-thread instruction conflicts. Also, the worst-case execution time (WCET) of applications running on multi-core processors estimated by our approach is much better than the estimation by simply assuming all L2 instruction accesses are misses.

Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches

  • Ding, Yiqiang;Zhang, Wei
    • Journal of Computing Science and Engineering
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    • v.7 no.4
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    • pp.285-299
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    • 2013
  • To enable hard real-time systems to take advantage of multicore processors, it is crucial to obtain the worst-case execution time (WCET) for programs running on multicore processors. However, this is challenging and complicated due to the inter-thread interferences from the shared resources in a multicore processor. Recent research used the combined cache conflict graph (CCCG) to model and compute the worst-case inter-thread interferences on a shared L2 cache in a multicore processor, which is called the CCCG-based approach in this paper. Although it can compute the WCET safely and accurately, its computational complexity is exponential and prohibitive for a large number of cores. In this paper, we propose three counter-based approaches to significantly reduce the complexity of the multicore WCET analysis, while achieving absolute safety with tightness close to the CCCG-based approach. The basic counter-based approach simply counts the worst-case number of cache line blocks mapped to a cache set of a shared L2 cache from all the concurrent threads, and compares it with the associativity of the cache set to compute the worst-case cache behavior. The enhanced counter-based approach uses techniques to enhance the accuracy of calculating the counters. The hybrid counter-based approach combines the enhanced counter-based approach and the CCCG-based approach to further improve the tightness of analysis without significantly increasing the complexity. Our experiments on a 4-core processor indicate that the enhanced counter-based approach overestimates the WCET by 14% on average compared to the CCCG-based approach, while its averaged running time is less than 1/380 that of the CCCG-based approach. The hybrid approach reduces the overestimation to only 2.65%, while its running time is less than 1/150 that of the CCCG-based approach on average.

Timing Analysis for Satellite Flight Software (인공위성 소프트웨어 타이밍 분석)

  • 이종인;최종욱;이재승;강수연
    • Proceedings of the Korean Information Science Society Conference
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    • 2003.10b
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    • pp.367-369
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    • 2003
  • 인공위성 탑재 소프트웨어는 정해진 시간 내에 필요한 작업을 수행하여야 하는 실시간 내장형 소프트웨어로 타이밍 분석이 중요하다. 기존의 인공위성소프트웨어 개발 시 적용되는 타이밍 분석기법은 개발자의 수작업에 의존하여 많은 시간과 노력이 요구되며 정확성에 문제가 있을 수 있는 단점이 있었다. 본 논문에서는 위성소프트에어의 타이밍 분석에 적용 가능한 최장 실행시간 (Worst Case Execution Time, WCET) 기법을 조사하고 보다 정확한 (tight) WCET를 구하기 위해 입력 데이터를 고려한 WCET 분석 방안을 제안한다.

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Static Worst-Case Execution Time Analysis Tool for Scheduling Primitives about Embedded OS (임베디드 운영체제의 스케줄링 프리미티브를 고려한 정적 최악실행시간 분석도구)

  • Park, Hyeon-Hui;Yang, Seung-Min;Choi, Yong-Hoon
    • Journal of KIISE:Computing Practices and Letters
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    • v.13 no.5
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    • pp.271-281
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    • 2007
  • Real-time support of embedded OS is not optional, but essential in contemporary embedded systems. In order to achieve these system#s real-time property, it is crucial that schedulability analysis for tasks having its property have been accomplished before system execution. Acquiring Worst-Case Execution Time(WCET) of task is a core part of schedulability analysis. Because traditional WCET tools analyze only its estimation of application task(i.e. program), it is not considered that application tasks are affected by scheduling primitives(e.g. scheduler, interrupt service routine, etc.) of OS when it schedules them. In this paper, we design and implement WCET analysis tool which deliberates on scheduling primitives of system using embedded Linux widely used in embedded OSes. This tool can estimate either WCET of normal application programs or corresponding primitives which have an influence on schduling property in embedded Linux kernel. Therefore, precision of estimation about schedulability analysis is improved. We develop this tool as Eclipse#s plug-in to work properly in any platform and support convenient interface or functionality for user.

Warp-Based Load/Store Reordering to Improve GPU Time Predictability

  • Huangfu, Yijie;Zhang, Wei
    • Journal of Computing Science and Engineering
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    • v.11 no.2
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    • pp.58-68
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    • 2017
  • While graphics processing units (GPUs) can be used to improve the performance of real-time embedded applications that require high throughput, it is challenging to estimate the worst-case execution time (WCET) of GPU programs, because modern GPUs are designed for improving the average-case performance rather than time predictability. In this paper, a reordering framework is proposed to regulate the access to the GPU data cache, which helps to improve the accuracy of the estimation of GPU L1 data cache miss rate with low performance overhead. Also, with the improved cache miss rate estimation, tighter WCET estimations can be achieved for GPU programs.

A Dynamic Storage Allocation Algorithm with Predictable Execution Time (예측 가능한 실행 시간을 가진 동적 메모리 할당 알고리즘)

  • Jeong, Seong-Mu;Yu, Hae-Yeong;Sim, Jae-Hong;Kim, Ha-Jin;Choe, Gyeong-Hui;Jeong, Gi-Hyeon
    • The Transactions of the Korea Information Processing Society
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    • v.7 no.7
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    • pp.2204-2218
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    • 2000
  • This paper proposes a dynamic storage allocation algorithm, QHF(quick-half-fit) for real-time systems. The proposed algorithm manages a free block list per each worked size for memory requests of small size, and a free block list per each power of 2 size for memory requests of large size. This algorithms uses the exact-fit policy for small sie requests and provides high memory utilization. The proposed algorithm also has the time complexity O(I) and enables us to easily estimate the worst case execution time (WCET). In order to confirm efficiency of the proposed algorithm, we compare he memory utilization of proposed algorithm with that of half-fit and binary buddy system that have also time complexity O(I). The simulation result shows that the proposed algorithm guarantees the constant WCET regardless of the system memory size and provides lower fragmentation ratio and allocation failure ratio thant other two algorithms.

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A Dynamic Voltage Scaling Algorithm for Aperiodic Tasks (비주기 태스크를 위한 동적 가변 전압 스케쥴링)

  • Kwon, Ki-Duk;Jung, Jun-Mo;Kwon, Sang-Hong
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.7 no.5
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    • pp.866-874
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    • 2006
  • This paper proposes a new Dynamic Voltage Scaling(DVS) algorithm to achieve low-power scheduling of aperiodic hard real-time tasks. Aperiodic tasks schedulingcannot be applied to the conventional DVS algorithm and result in consuming energy more than periodic tasks because they have no period, non predictable worst case execution time, and release time. In this paper, we defined Virtual Periodic Task Set(VTS) which has constant period and worst case execution time, and released aperiodic tasks are assigned to this VTS. The period and worst case execution time of the virtual task can be obtained by calculating task utilization rate of both periodic and aperiodic tasks. The proposed DVS algorithm scales the frequency of both periodic and aperiodic tasks in VTS. Simulation results show that the energy consumption of the proposed algorithm is reduced by 11% over the conventional DVS algorithm for only periodic task.

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Scratchpad Memory Architectures and Allocation Algorithms for Hard Real-Time Multicore Processors

  • Liu, Yu;Zhang, Wei
    • Journal of Computing Science and Engineering
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    • v.9 no.2
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    • pp.51-72
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    • 2015
  • Time predictability is crucial in hard real-time and safety-critical systems. Cache memories, while useful for improving the average-case memory performance, are not time predictable, especially when they are shared in multicore processors. To achieve time predictability while minimizing the impact on performance, this paper explores several time-predictable scratch-pad memory (SPM) based architectures for multicore processors. To support these architectures, we propose the dynamic memory objects allocation based partition, the static allocation based partition, and the static allocation based priority L2 SPM strategy to retain the characteristic of time predictability while attempting to maximize the performance and energy efficiency. The SPM based multicore architectural design and the related allocation methods thus form a comprehensive solution to hard real-time multicore based computing. Our experimental results indicate the strengths and weaknesses of each proposed architecture and the allocation method, which offers interesting on-chip memory design options to enable multicore platforms for hard real-time systems.

A Real-time Dynamic Storage Allocation Algorithm Supporting Various Allocation Policies (다양한 할당 정책을 지원하는 실시간 동적 메모리 할당 알고리즘)

  • 정성무
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.10B
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    • pp.1648-1664
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    • 2000
  • This paper proposes a real-time dynamic storage allocation algorithm QSHF(quick-segregated-half-fit) that provides various memory allocation policies. that manages a free block list per each word size for memory requests of small size good(segregated)-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per proper range size for medium size requests and half-fit policy that manages a free list per each power of 2 size for large size requests. The proposed algorithm has the time complexit O(1) and makes us able to easily estimate the worst case execution time(WCET). This paper also suggests two algorithm that finds the proper free list for the requested memory size in predictable time and if the found list is empty then finds next available non-empty free list in fixed time. In order to confirm efficiency of the proposed algorithm we simulated the memory utilization of each memory allocation policy. The simulation result showed that each policy guarantees the constant WCET regardless of memory size but they have trade-off between memory utilization and list management overhead.

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