• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.3B
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• pp.65-71
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• 2005

The primary function of the Internet routers is to forward incoming packets toward their final destinations. IP address lookup is one of the most important functions in evaluating router performance since IP address lookup should be performed in wire-speed for the hundred-millions of incoming packets per second. With CIDR, the IP prefixes of routing table have arbitrary lengths, and hence address lookup by exact match is no longer valid. As a result, when packets arrive, routers compare the destination IP addresses of input packets with all prefixes in its routing table and determine the most specific entry among matching entries, and this is called the longest prefix matching. In this paper, based on parallel multiple hashing and prefix grouping, we have proposed a hardware architecture which performs an address lookup with a single memory access.

• The KIPS Transactions:PartC
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• v.18C no.3
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• pp.179-186
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• 2011

Wireless Mesh Network technology refers to the technology which establishes wireless network whose transmission speed is similar to that of the wire system, and provides more enhanced flexibility in the building of network, compared to the existing wired network. In addition, it has the feature of less mobility and less restriction from the energy effect. However, there follow many considerations such as system overhead in the case of setting or the selection of multi-path. Accordingly, the focus is on the design and optimization of network which can reflect this network feature and the technology to establish path. This paper suggests the methods on the programming of path in Wireless Mesh Network routing by applying the evaluation value of node service, making use of the loss rate of data, the hop count of bandwidth and link and the traffic status of node, considering the performance of link and load in the fitness evaluation function, in order to respond to the programming of multi-path effectively.

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.440-443
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• 2001

As inter-network traffics grows rapidly, the router systems as a network component becomes to be capable of not only wire-speed packet processing but also plentiful programmability for quality services. A network processor technology is widely used to achieve such capabilities in the high-end router. Although providing two such capabilities, the network processor can't support a deep packet processing at nominal wire-speed. Considering QoS may result in performance degradation of processing packet. In order to achieve foster processing, one chipset of network processor is occasionally not enough. Using more than one urges to consider a problem that is, for instance, an out-of-order delivery of packets. This problem can be serious in some applications such as voice over IP and video services, which assume that packets arrive in order. It is required to develop an effective packet processing mechanism leer using more than one network processors in parallel in one linecard unit of the router system. Simulation analysis is also needed for verifying the mechanism. We propose the packet processing mechanism consisting of more than two NPs in parallel. In this mechanism, we use a load-balancing algorithm that distributes the packet traffic load evenly and keeps the sequence, and then verify the algorithm with simulation analysis. As a simulation tool, we use DEVSim++, which is a DEVS formalism-based hierarchical discrete-event simulation environment developed by KAIST. In this paper, we are going to show not only applicability of the DEVS formalism to hardware modeling and simulation but also predictability of performance of the load balancer when implemented with FPGA.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8B
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• pp.691-700
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• 2006

Based on the destination IP address of incoming packets, the Internet routers determine next hops and forward packets toward final destinations through If address lookup. The bandwidth of communication links increases exponentially fast as well as the routing table size grows significant as the number of single host networks attached to the Internet increases. Since packets should be processed at wire-speed, the increased link speed reduces the processing time of a packet in routers, and hence more efficient and fast IP address lookup algorithms and architectures are required in the next generation routers. Most of the previous IP lookup schemes compare routing prefixes of shorter length first with a given input IP address. Since IP address lookup needs to find the most specific route of the given input, search continues until the longest matched prefix is found while it keeps remembering the current test matching prefix. In this paper, based on binary search on prefix length, we proposed a new IP address lookup algorithm which compares longer prefixes first. The proposed scheme is consisted of multiple tries with prefixes on leaves only. The trie composed of the longest prefixes is primarily searched whether there is a match with the given input. This processing is repeated for the trio of the next longer prefixes until there finds a match. Hence the proposed algorithm provides the fast search speed. The proposed algorithm also provides the incremental update of prefixes while the previous binary search on length scheme does not provide the incremental update because of pre-processing requirement. In this paper, we performed extensive simulations and showed the performance comparisons with related works.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.