• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.1038-1041
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• 2003

In the paper, we investigated silicon surface microstructures formed by reactive ion etching in hollow cathode system. Wet anisotropic chemical etching technique use to form random pyramidal structure on <100> silicon wafers usually is not effective in texturing of low-cost multicrystalline silicon wafers because of random orientation nature, but High density hollow cathode plasma system illustrates high deposition rate, better film crystal structure, improved etching characteristics. The etched silicon surface is covered by columnar microstructures with diameters form 50 to 100nm and depth of about 500nm. We used $SF_{6}$ and $O_{2}$ gases in HCP dry etch process. This paper demonstrates very high plasma density of $2{\times}10^{12}$ $cm^{-3}$ at a discharge current of 20 mA. Silicon etch rate of 1.3 ${\mu}s/min$. was achieved with $SF_{6}/O_{2}$ plasma conditions of total gas pressure=50 mTorr, gas flow rate=40 sccm, and rf power=200 W. Our experimental results can be used in various display systems such as thin film growth and etching for TFT-LCDs, emitter tip formations for FEDs, and bright plasma discharge for PDP applications. In this paper we directed our study to the silicon etching properties such as high etching rate, large area uniformity, low power with the high density plasma.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.319.1-319.1
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• 2016

Recently, the Al-doped ZnO (ZnO:Al) films are intensively used in thin film a-Si solar cell applications due to their high transmittance and good conductivity. The textured ZnO:Al films are used to enhance the light trapping in thin film solar cells. The wet etch process is used to texture ZnO:Al films by dipping in diluted acidic solutions like HCl or HF. During that process the glass substrate could be damaged by the acidic solution and it may be difficult to apply it for the inline mass production process since it has to be done outside the chamber. In this paper we report a new technique to control the surface morphology of RF-sputtered ZnO:Al films. The ZnO:Al films are textured with vaporized HF formed by the mixture of HF and H2SiO3 solution. Even though the surface of textured ZnO:Al films by vapor etching process showed smaller and sharper surface structures compared to that of the films textured by wet etching, the haze value was dramatically improved. We achieved the high haze value of 78% at the wavelength of 540 nm by increasing etching time and HF concentration. The haze value of about 58% was achieved at the wavelength of 800 nm when vapor texturing was used. The ZnO:Al film texture by HCl had haze ratio of about 9.5 % at 800 nm and less than 40 % at 540 nm. In addition to low haze ratio, the texturing by HCl was very difficult to control etching and to keep reproducibility due to its very fast etching speed.

• Journal of Sensor Science and Technology
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• v.3 no.2
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• pp.74-80
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• 1994

Silicon direct bonding technology is very attractive for both silicon-on-insulator devices and sensor fabrication because of its thermal stress free structure and stability. The process of SDB includes hydration of silicon wafer and heat treatment in a wet oxidation furnace. After hydration process, hydroxyl groups of silicon wafer were analyzed by using Fourier transformation-infrared spectroscopy. In case of hydrophilic treatment using a ($H_{2}O_{2}\;:\;H_{2}SO_{4}$) solution, hydroxyl groups are observed in a broad band around the 3474 $cm^{-1}$ region. However, hydroxyl groups do not appear in case of diluted HF solution. The bonded wafer was etched by using tetramethylammonium hydroxide etchant. The surface of the self etch-stopped silicon dioxide is completely flat, so that it can be used as sensor applications such as pressure, flow and acceleration, etc..

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.107-107
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• 2003

원자층 증착(ALD, Atomic Layer Deposition)기술은 기판 표면에서의 self-limiting reaction을 통해 매우 얇은 박막을 형성할 수 있고, 두께 및 조성 제어를 정확히 할 수 있으며, 복잡한 형상의 기판에서도 100%에 가까운 step coverage를 얻을 수 있어 초미세패턴의 형성과 매우 얇은 두께에서 균일한 물리적, 전기적 특성이 요구되는 초미세 반도체 공정에 적합하다. 특히 반도체의 logic 및 memory 소자의 gate 공정에서 절연막과 보호막으로, 그리고 배선공정에서는 층간절연막(ILD, Inter Layer Dielectric)으로 사용하는 silicon oxide 박막에 적용될 경우, LPCVD 방법에 비해 낮은 온도에서 증착이 가능해 boron과 같은 dopant들의 확산을 최소화하여 transistor 특성 향상이 가능하며, PECVD 방법에 비해 전기적·물리적 특성이 월등히 우수하고 대면적 uniformity 증가가 기대된다. 본 연구에서는 자체적으로 설계 및 제작한 장비를 이용하여 silicon oxide 박막을 ALD 방법으로 증착하고 그 특성을 살펴보았다. 먼저, cycle 수에 따른 증착 박막 두께의 linearity를 통해서 원자층 증착(ALD)임을 확인할 수 있었으며, reactant exposure(L)와 증착 온도에 따른 deposition rate 변화를 알아보았다 Elipsometer를 이용해 증착된 silicon oxide 박막의 두께 및 굴절률과 그 uniformity를 관찰하였고, AES 및 XPS 분석 장비로 박막의 조성비와 불순물 성분을 살펴보았으며, 증착 박막의 치밀성 평가를 위해 HF etchant로 wet etch rate를 측정하여 물리적 특성을 정리하였다. 특히, 기존의 박막 증착 방법인 LPCVD와 PECVD에 의한 silicon oxide박막의 물성과 비교, 평가해 보았다. 나아가 적절한 촉매 물질을 선정하여 원자층 증착(ALD) 공정에 적용하여 그 효과도 살펴보았다.

• Journal of the Semiconductor & Display Technology
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• v.5 no.2 s.15
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• pp.47-49
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• 2006

Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.

• Laser Solutions
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• v.17 no.4
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• pp.20-23
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• 2014

In printed electronics, printing rolls are used to transfer electronic ink onto a flexible substrate. Generally printing rolls are patterned in microscale by the indirect laser method. Since based on the wet etch process, the indirect method is neither environment-friendly nor suitable for making a printing roll with patterns narrower than $20{\mu}m$. In this paper, we have directly engraved micro-patterns into a Zn-coated metal specimens using a picosecond laser in order both to engrave $10{\mu}m$-wide patterns and to improve the pattern profile. Experiments showed that it is possible to engrave $10{\mu}m$-wide patterns with an a rectangular-shaped profile which is necessary for the dimensionally accurate printing.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.4
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• pp.38-48
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• 1992

OEIC(Optoelectronic Integrated Circuit)'s can be integrated horizontally or vertically. Horizontal integration approach is, however, more immune to parasitic and more universally applicable. In this paper, a structural modeling, fabrication and characterization of PIN photodiodes which can be used in the horizontal integration are performed. For device modeling, we build a transmission line model from 2-D device simulation, from which lumped model parameters are extracted. The speed limits of the PIN photodiodes can also be calculated under various structural conditions from the model. Thus optimum design of horizontally integrated PIN photodiodes for high speed operation are possible. Such InGaAs/InP PIN photodiodes for long-wavelength communications are fabricated using pit etch, epi growth, planarization, diffusion and metallization processes. Planarization process using both RIE and wet etching and diffusion process using evaporated Zn$_{3}P_{2}$ film are developed. Characterization of the fabricated devices is performed through C-V and I-V measurements. At a reserve bias of 10V, the dark current is less than 5nA and capacitance is about 0.4pF. The calculated bandwidth using the measured series resistance and capacitance is about 4.23GHz.

• Journal of Biomedical Engineering Research
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• v.29 no.5
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• pp.392-399
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• 2008

Thin-film transistor (TFT) arrays for an x-ray detector require quite different design concept from that of the conventional active-matrix liquid crystal devices (AM-LCDs). In this paper anew design of TFT array which uses only SiNx for passivation layer is described to meet the detector performance and the product availability simultaneously. For the purpose of optimizing the design parameters of the TFT array, a Spice simulation was performed. As a result, some parameters, such as the TFT width, the data line capacitance, and the storage capacitance, were able to be fixed. The other parameters were decided within a permissible range of the TFT process especially the photolithography process and the wet etch process. Then we adapted the TFT array which had been produced by the proposed design to our prototype model (FDXD-1417 and evaluated it clinically by comparing with a commercial model (EPEX, Hologic, Beford, USA). The results say that our prototype model is slightly better than EPEX system in chest PA images. So we can prove the technical usefulness and the commercial values of the proposed TFT design.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.4
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• pp.309-317
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• 2000

Langasite is a promising new piezoelectric material for SAW filter application. Little was known until recently about the methods needed to mechanically polish and chemically polish/etch this material. In this experiment, polishing, slurry chemistry and chemical wet etching for langasite is described. Conventional quartz and LN ($LiNbO_3$) polishing methods did not produce satisfactory polished surfaces, and polishing with a colloidal silica slurries has shown to be most effective. The optimum condition was investigated by changing the slurry chemistry. As the planarization effect is very important in SAW filter applications, the examination of the effective particle number effect and the particle size effect was carried out. Z-cut langasite surface which had been polished with the colloidal silica slurries was etched in a variety of etchants. Conventional quartz etchants destroyed the polished surface. Other etchants formed a thin film on the surfaces. In this experiment, the reaction between langasite and a few etching solution was analysed. And an appropriate selective etchant solution for analyzing the defects was synthesized.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.4
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• pp.325-331
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• 2007

In this study, the inter-metal dielectric material of FSG was changed by low-k material in $0.13{\mu}m$ foundry-compatible technology (FCT) device process based on fluorinated silicate glass (FSG). Black diamond (BD) was used as a low-k material with a dielectric constant of 2.95 for optimization and yield-improvement of the low-k based device process. For yield-improvement in low-k based device process, some problems such as photoresist (PR) poisoning, damage of low-k in etch/ash/cleaning process, and chemical mechanical planarization (CMP) delamination must be solved. The PR poisoning was not observed in BD based device. The pressure in CMP process decreased to 2.8 psi to remove the CMP delamination for Cu-CMP and USG-CMP. $H_2O$ ashing process was selected instead of $O_2$ ashing process due to the lowest condition of low-k damage. NE14 cleaning after ashing process lot the removal of organic residues in vias and trenches was employed for wet process instead of dilute HF (DHF) process. The similar-state of SRAM yield was obtained in Cu/low-k process compared with the conventional $0.13{\mu}m$ FCT device by the optimization of these process conditions.