• Korean Chemical Engineering Research
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• 제50권2호
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• pp.211-216
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• 2012

염화제이철 수용액에 의한 스테인레스 강판의 식각반응에 관한 연구를 수행하였다. 식각액 교반속도, 식각온도, $Fe^{3+}$ 이온 농도, 식각액의 유리산도 및 비중 등 여러 공정변수가 식각속도에 미치는 영향에 대해 조사하였고, 그 결과, AK(aluminum-killed) 철, 크롬(chlomium) 강, 그리고 스테인레스 강(STS430J1L 합금)의 식각반응이 1차 반응식을 잘 따름을 알 수 있었다. 또한 식각액의 피로도(fatigue ratio)가 16% 이하로 유지되면 식각액 내에 슬러지가 발생하지 않으며, 식각된 강판의 표면거칠기 또한 좋아짐을 알 수 있었다. 본 연구에서 조사한 범위 내에서는, 식각액의 보메(Baume)가 증가하면 식각속도는 감소하나 유리산도가 식각속도에 미치는 영향은 미비함을 알 수 있었다. 한편 본 연구의 실험결과는 공정모델링을 통해 유도된 식각속도식의 계산결과와 잘 일치함을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.150-150
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• 2008

본 연구에서는 Wet chemistry damage가 Nanopatterned p-ohmic electrode에 미치는 영향을 연구하였다. Nanopattern은 Metal clustering을 이용하여, P-GaN와 Ohmic형성에 유리한 Pd을 50$\AA$ 적층한 후 Rapid Thermal Annealing방법으로 $850^{\circ}C$, $N_2$분위기에서 3min열처리를 하여 Pd Clustering mask 를 제작하였다. Wet etching은 $85^{\circ}C$, $H_3PO_4$조건에서 시간에 따라 Sample을 Dipping하는 방법으로 시행하였다 Ohmic test를 위해서 Circular - Transmission line Model 방법을 이용하였으며, Atomic Force Microscopy과 Parameter Analyzer로 Nanopatterned GaN surface위에 형성된 Ni/ Au Contact에서의 전기적 분석과, 표면구조분석을 시행하였다. AFM결과 Wet처리시간에 따라서 Etching형상 및 Etch rate이 영향을 받는 것이 확인되었고, Ohmic test에서 Wet chemistry처리에 의한 Tunneling parameter와 Schottky Barrier Height가 크게 증/감함을 관찰하였다. 이러한 결과들은 Wet처리에 의해서 발생된 Defect가 GaN의 표면과 하부에서 발생되며, Deep acceptor trap 및 transfer거동과 밀접한 관련이 있음을 확인 할 수 있었다. 보다 자세한 Transport 및 Wet chemical처리영향에 관한 형성 Mechanism은 후에 I-V-T, I-V, C-V, AFM결과 들을 활용하여 발표할 예정이다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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• pp.232.2-232.2
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• 2014

Since its discovery in 2004, graphene, a sp2-hybridized 2-Dimension carbon material, has drawn enormous attention. A variety of approaches have been attempted, such as epitaxial growth from silicon carbide, chemical reduction of graphene oxide and CVD. Among these approaches, the CVD process takes great attention due to its guarantee of high quality and large scale with high yield on various transition metals. After synthesis of graphene on metal substrate, the subsequent transfer process is needed to transfer graphene onto various target substrates, such as bubbling transfer, renewable epoxy transfer and wet etching transfer. However, those transfer processes are hard to control and inevitably induce defects to graphene film. Especially for wet etching transfer, the metal substrate is totally etched away, which is horrendous resources wasting, time consuming, and unsuitable for industry production. Thus, our group develops one-step process to directly grow graphene on glass substrate in plasma enhanced chemical vapor deposition (PECVD). Copper foil is used as catalyst to enhance the growth of graphene, as well as a temperature shield to provide relatively low temperature to glass substrate. The effect of growth time is reported that longer growth time will provide lower sheet resistance and higher VSG flakes. The VSG with conductivity of $800{\Omega}/sq$ and thickness of 270 nm grown on glass substrate can be obtained under 12 min growing time. The morphology is clearly showed by SEM image and Raman spectra that VSG film is composed of base layer of amorphous carbon and vertically arranged graphene flakes.

• 한국정밀공학회지
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• 제21권4호
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• pp.24-31
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• 2004

The objective of this work is to suggest a mastless pattern fabrication technique using the combination of machining by Nanoindenter(equation omitted) XP and HF wet etching. Sample line patterns were machined on a borosilicate surface by constant load scratch (CLS) of the Nanoindenter(equation omitted) XP with a Berkovich diamond tip, and they were etched in HF solution to investigate chemical characteristics of the machined borosilicate surface. All morphological data of scratch traces were scanned using atomic force microscope (AFM).

• 한국결정성장학회:학술대회논문집
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• 한국결정성장학회 1996년도 The 9th KACG Technical Annual Meeting and the 3rd Korea-Japan EMGS (Electronic Materials Growth Symposium)
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• pp.494-496
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• 1996

The purpose of this study is to investigate the effect of process conditions on pore distribution in porous silicon layer prepared by electrochemical reaction. Porous silicon layers formed on p-type silicon wafer show the network structure of fine porse whose diameters are less than 100${\AA}$. In n-type porous silicon, selective growth was found on the pore surface by wet etching process after PR patterning. And numerical method showed high current density on the pore tip. With this result we confirmed that pore formation has two steps. First step is the initial attack on the surface and second step is the directional growth on the pore tip.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2007년도 제33회 하계학술대회 초록집
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• pp.282-282
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• 2007

• 한국전기전자재료학회논문지
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• 제18권12호
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• pp.1075-1079
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• 2005

The Pseudo MOSFET measurements technique has been used for the electrical characterization of the nano SOI wafer. Silicon islands for the Pseudo MOSFET measurements were fabricated by selective etching of surface silicon film with dry or wet etching to examine the effects of the etching process on the device properties. The characteristics of the Pseudo MOSFET were not changed greatly in the case of thick SOI film which was 205 nm. However the characteristics of the device were dependent on etching process in the case of less than 100 nm thick SOI film. The sub 100 nm SOI was obtained by thinning the silicon film of standard thick SOI wafer. The thickness of SOI film was varied from 88 nm to 44 nm by chemical etching. The etching process effects on the properties of pseudo MOSFET characteristics, such as mobility, turn-on voltage, and drain current transient. The etching Process dependency is greater in the thinner SOI wafer.

• 소성∙가공
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• 제13권4호
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• pp.326-333
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• 2004

The nanoprobe based on lithography, mainly represented by SPM based technologies, has been recognized as a potential application to fabricate the surface nanosctructures because of its operational versatility and simplicity. However, nanoprobe based on lithography itself is not suitable for mass production because it is time a consuming method and not economical for commercial applications. One solution is to fabricate a mold that will be used for mass production processes such as nanoimprint, PDMS casting, and others. The objective of this study is to fabricate the silicon stamper for PDMS casting process by a mastless fabrication technique using the combination of nano/micro machining by Nanoindenter XP and KOH wet etching. Effect of the Berkovich tip alignment on the deformation was investigated. Grooves were machined on a silicon surface, which has native oxide on it, by constant load scratch (CLS), and they were etched in KOH solutions to investigate chemical characteristics of the machined silicon surface. After the etching process, the convex structures was made because of the etch mask effect of the mechanically affected layer generated by nanoscratch. On the basis of this fact, some line patterns with convex structures were fabricated. Achieved groove and convex structures were used as a stamper for PDMS casting process.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.401-401
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• 2011

In this work, we deposited Al2O3doped ZnO (AZO) thin films by direct current (DC) magnetron sputtering method with a $40^{\circ}$ tilted target, for application in the front layer of thin film solar cell. Wet chemical etching behavior of AZO films was also investigated. In order to optimize textured AZO films, oxalic acid ($C_2H_2O_4$)has been used as wet etchant of AZO film. In this experiment we used 0.001% concentration of oxalic acid various etching time, that showed an anisotropy in etching texture of AZO films. Electrical resistivity, Hall mobility and carrier concentration measurements are performed by using the Hall measurement, that are $6{\times}10^{-4}{\Omega}cm$, $20{\sim}25cm^2/V-s$ and $4{\sim}6{\times}10^{20}$, respectively.

• 반도체디스플레이기술학회지
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• 제8권1호
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• pp.1-5
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• 2009

Typically, single-wafer wet etching is done by dispensing chemical onto the front and back side of spin wafer. The wafer is fixed by a number of chuck pins, which obstruct the chemical flow and would result in the incomplete removal of the remaining film, which can become a source of contamination in the next process. In this paper, we introduce a novel design of wafer chuck, in which chuck pins are groupped into two and each group of pins fixes the substrate alternatively. Two groups of chuck pins fix the high-speed spin substrate with non contact method using a magnetic material. The actual process has been executed to observe the effectiveness of this new wafer chuck. It was found that the new wafer chuck performed better than the conventional wafer chuck for removing the remaining film from the bevel and edge side of substrate.